參數(shù)資料
型號(hào)： E28F320J3A-125
廠商： Intel Corp.
英文描述： Intel StrataFlash Memory (J3)
中文描述： 英特爾StrataFlash存儲(chǔ)器（J3）
文件頁(yè)數(shù)： 14/58頁(yè)
文件大?。?/td> 380K
代理商： E28F320J3A-125
28F128J3A, 28F640J3A, 28F320J3A
8
Preliminary
3.1
Read
Information can be read from any block, query, identifier codes, or status register independent of
the V
PEN
voltage.
Upon initial device power-up or after exit from reset/power-down mode, the device automatically
resets to read array mode. Otherwise, write the appropriate read mode command (Read Array, Read
Query, Read Identifier Codes, or Read Status Register) to the CUI. Six control pins dictate the data
flow in and out of the component: CE
0
, CE
1
, CE
2
, OE#, WE#, and RP#. The device must be
enabled (see
Table 2,
“
Chip Enable Truth Table
”
on page 7
), and OE# must be driven active to
obtain data at the outputs. CE
0
, CE
1
, and CE
2
are the device selection controls and, when enabled
(see
Table 2
), select the memory device. OE# is the data output (DQ
0
–
DQ
15
) control and, when
active, drives the selected memory data onto the I/O bus. WE# must be at V
IH
.
When reading information in read array mode, the device defaults to asynchronous page mode.
This mode provides high data transfer rate for memory subsystems. In this state, data is internally
read and stored in a high-speed page buffer. A
2:0
addresses data in the page buffer. The page size is
four words or eight bytes. Asynchronous word/byte mode is supported with no additional
commands required.
3.2
Output Disable
With OE# at a logic-high level (V
IH
), the device outputs are disabled. Output pins DQ
0
–
DQ
15
are
placed in a high-impedance state.
3.3
Standby
CE
0
, CE
1
, and CE
2
can disable the device (see
Table 2
) and place it in standby mode which
substantially reduces device power consumption. DQ
0
–
DQ
15
outputs are placed in a high-
impedance state independent of OE#. If deselected during block erase, program, or lock-bit
configuration, the WSM continues functioning, and consuming active power until the operation
completes.
3.4
Reset/Power-Down
RP# at V
IL
initiates the reset/power-down mode.
In read modes, RP#-low deselects the memory, places output drivers in a high-impedance state, and
turns off numerous internal circuits. RP# must be held low for a minimum of t
PLPH
. Time t
PHQV
is
required after return from reset mode until initial memory access outputs are valid. After this wake-
up interval, normal operation is restored. The CUI is reset to read array mode and status register is
set to 80H.
During block erase, program, or lock-bit configuration modes, RP#-low will abort the operation. In
default mode, STS transitions low and remains low for a maximum time of t
PLPH
+ t
PHRH
until the
reset operation is complete. Memory contents being altered are no longer valid; the data may be
partially corrupted after a program or partially altered after an erase or lock-bit configuration. Time
t
PHWL
is required after RP# goes to logic-high (V
IH
) before another command can be written.
相關(guān)PDF資料
PDF描述
E28F320J3A-150 Intel StrataFlash Memory (J3)
E28F320J3C-115 Intel StrataFlash Memory (J3)
E28F320J3C-120 Intel StrataFlash Memory (J3)
E28F320J3C-125 Intel StrataFlash Memory (J3)
E28F320J3C-150 Intel StrataFlash Memory (J3)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
E28F320J3A-150 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Memory (J3)
E28F320J3C-110 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Memory (J3)
E28F320J3C-115 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Memory (J3)
E28F320J3C-120 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Memory (J3)
E28F320J3C-125 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Memory (J3)
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