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SAM4CP [DATASHEET]
43051E–ATPL–08/14
12.4.2.7 Synchronization Primitives
The Cortex-M4 instruction set includes pairs of
synchronization primitives
. These provide a non-blocking mechanism that
a thread or process can use to obtain exclusive access to a memory location. The software can use them to perform a
guaranteed read-modify-write memory update sequence, or for a semaphore mechanism.
A pair of synchronization primitives comprises:
A Load-exclusive Instruction
, used to read the value of a memory location, requesting exclusive access to that
location.
A Store-Exclusive instruction
, used to attempt to write to the same memory location, returning a status bit to a register.
If this bit is:
0: It indicates that the thread or process gained exclusive access to the memory, and the write succeeds.
1: It indicates that the thread or process did not gain exclusive access to the memory, and no write is performed.
The pairs of Load-Exclusive and Store-Exclusive instructions are:
The word instructions LDREX and STREX.
The halfword instructions LDREXH and STREXH.
The byte instructions LDREXB and STREXB.
The software must use a Load-Exclusive instruction with the corresponding Store-Exclusive instruction.
To perform an exclusive read-modify-write of a memory location, the software must:
1.
2.
3.
4.
Use a Load-Exclusive instruction to read the value of the location.
Update the value, as required.
Use a Store-Exclusive instruction to attempt to write the new value back to the memory location.
Test the returned status bit. If this bit is:
0: The read-modify-write completed successfully.
1: No write was performed. This indicates that the value returned at step 1 might be out of date. The software must
retry the read-modify-write sequence.
The software can use the synchronization primitives to implement a semaphore as follows:
1.
2.
3.
Use a Load-Exclusive instruction to read from the semaphore address to check whether the semaphore is free.
If the semaphore is free, use a Store-Exclusive instruction to write the claim value to the semaphore address.
If the returned status bit from step 2 indicates that the Store-Exclusive instruction succeeded then the software has
claimed the semaphore. However, if the Store-Exclusive instruction failed, another process might have claimed the
semaphore after the software performed the first step.
The Cortex-M4 includes an exclusive access monitor, that tags the fact that the processor has executed a Load-Exclu-
sive instruction. If the processor is part of a multiprocessor system, the system also globally tags the memory locations
addressed by exclusive accesses by each processor.
The processor removes its exclusive access tag if:
It executes a CLREX instruction.
It executes a Store-Exclusive instruction, regardless of whether the write succeeds.
An exception occurs. This means that the processor can resolve semaphore conflicts between different threads.
In a multiprocessor implementation:
Executing a CLREX instruction removes only the local exclusive access tag for the processor.
Executing a Store-Exclusive instruction, or an exception, removes the local exclusive access tags, and all global
exclusive access tags for the processor.
For more information about the synchronization primitive instructions, see
“LDREX and STREX”
and
“CLREX”
.