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SAM4CP [DATASHEET]
43051E–ATPL–08/14
Fault Status Registers and Fault Address Registers
The fault status registers indicate the cause of a fault. For bus faults and memory management faults, the fault address
register indicates the address accessed by the operation that caused the fault, as shown in
Table 12-12
.
Lockup
The processor enters a lockup state if a hard fault occurs when executing the NMI or hard fault handlers. When the pro-
cessor is in lockup state, it does not execute any instructions. The processor remains in lockup state until either:
It is reset.
An NMI occurs.
It is halted by a debugger.
Note:
If the lockup state occurs from the NMI handler, a subsequent NMI does not cause the processor to leave the
lockup state.
12.5
Power Management
The Cortex-M4 processor
sleep modes reduce the power consumption:
Sleep mode stops the processor clock.
Deep sleep mode stops the system clock and switches off the PLL and flash memory.
The SLEEPDEEP bit of the SCR selects which sleep mode is used; see
“System Control Register”
.
This section describes the mechanisms for entering sleep mode, and the conditions for waking up from sleep mode.
12.5.1 Entering Sleep Mode
This section describes the mechanisms software can use to put the processor into sleep mode.
The system can generate spurious wakeup events, for example a debug operation wakes up the processor. Therefore,
the software must be able to put the processor back into sleep mode after such an event. A program might have an idle
loop to put the processor back to sleep mode.
12.5.1.1 Wait for Interrupt
The
wait for interrupt
instruction, WFI, causes immediate entry to sleep mode. When the processor executes a WFI
instruction it stops executing instructions and enters sleep mode. See
“WFI”
for more information.
12.5.1.2 Wait for Event
The
wait for event
instruction, WFE, causes entry to sleep mode conditional on the value of an one-bit event register.
When the processor executes a WFE instruction, it checks this register:
If the register is 0, the processor stops executing instructions and enters sleep mode.
If the register is 1, the processor clears the register to 0 and continues executing instructions without entering
sleep mode.
See
“WFE”
for more information.
Table 12-12. Fault Status and Fault Address Registers
Handler
Status Register
Name
Address Register
Name
Register Description
Hard fault
SCB_HFSR
-
“Hard Fault Status Register”
Memory
management fault
MMFSR
SCB_MMFAR
“MMFSR: Memory Management Fault Status
Subregister”
“MemManage Fault Address Register”
Bus fault
BFSR
SCB_BFAR
“BFSR: Bus Fault Status Subregister”
“Bus Fault Address Register”
Usage fault
UFSR
-
“UFSR: Usage Fault Status Subregister”