參數(shù)資料
型號(hào)： EDE1104ABSE-8E-E
廠商： ELPIDA MEMORY INC
元件分類： DRAM
英文描述： 1G bits DDR2 SDRAM
中文描述： 256M X 4 DDR DRAM, 0.4 ns, PBGA68
封裝： ROHS COMPLIANT, FBGA-68
文件頁(yè)數(shù)： 32/82頁(yè)
文件大?。?/td> 618K
代理商： EDE1104ABSE-8E-E
EDE1104ABSE, EDE1108ABSE, EDE1116ABSE
Data Sheet E0852E50 (Ver. 5.0)
32
Command Operation
Command Truth Table
The DDR2 SDRAM recognizes the following commands specified by the /CS, /RAS, /CAS, /WE and address pins.
CKE
Function
Symbol
Previous
cycle
Current
cycle
/CS
/RAS
/CAS
/WE BA0 BA1 BA2
A13 to
A11
A10
A0 to
A9
Notes
Mode register set
Extended mode
register set (1)
Extended mode
register set (2)
Auto-refresh
MRS
H
H
L
L
L
L
L
L
L
MRS OPCODE
EMRS (1)
OPCODE
EMRS (2)
OPCODE
×
×
1
EMRS(1)
H
H
L
L
L
L
H
L
L
1
EMRS(2)
H
H
L
L
L
L
L
H
L
1
REF
H
H
L
L
L
H
×
×
×
×
1
Self-refresh entry
SELF
H
L
L
L
L
H
×
×
×
×
×
×
1
Self-refresh exit
SELFX
L
H
H
×
×
×
×
×
×
×
×
×
1, 6
L
H
L
H
H
H
×
×
×
×
×
×
Single bank precharge
PRE
H
H
L
L
H
L
BA
×
L
×
1, 2
Precharge all banks
PALL
H
H
L
L
H
L
×
×
×
×
H
×
1
Bank activate
ACT
H
H
L
L
H
H
BA
RA
1, 2, 7
Write
WRIT
H
H
L
H
L
L
BA
CA
L
CA
1, 2, 3
Write with auto precharge
WRITA
H
H
L
H
L
L
BA
CA
H
CA
1, 2, 3
Read
READ
H
H
L
H
L
H
BA
CA
L
CA
1, 2, 3
Read with auto precharge READA
H
H
L
H
L
H
BA
CA
H
CA
1, 2, 3
No operation
NOP
H
×
L
H
H
H
×
×
×
×
×
×
1
Device deselect
DESL
H
×
H
×
×
×
×
×
×
×
×
×
1
Power-down mode entry
PDEN
H
L
H
×
×
×
×
×
×
×
×
×
1, 4
H
L
L
H
H
H
×
×
×
×
×
×
Power-down mode exit
PDEX
L
H
H
×
×
×
×
×
×
×
×
×
1, 4
Remark: H = VIH. L = VIL.
×
= VIH or VIL. BA = Bank Address, RA = Row Address , CA = Column Address
Notes: 1. All DDR2 commands are defined by states of /CS, /RAS, /CAS, /WE and CKE at the rising edge of the
clock.
2. Bank select (BA0, BA1 and BA2), determine which bank is to be operated upon.
3. Burst reads or writes should not be terminated other than specified as
″
Reads interrupted by a Read
″
in
burst read command [READ] or
″
Writes interrupted by a Write
″
in burst write command [WRIT].
4. The power-down mode does not perform any refresh operations. The duration of power-down is therefore
limited by the refresh requirements of the device. One clock delay is required for mode entry and exit.
5. The state of ODT does not affect the states described in this table. The ODT function is not available
during self-refresh.
6. Self-refresh exit is asynchronous.
7. 8-bank device sequential bank activation restriction: No more than 4 banks may be activated in a rolling
tFAW window. Converting to clocks is done by dividing tFAW (ns) by tCK (ns) and rounding up to next
integer value. As an example of the rolling window, if (tFAW/tCK) rounds up to 10 clocks, and an activate
command is issued in clock N, no more than three further activate commands may be issued in clock N+1
through N+9.
L
H
L
H
H
H
×
×
×
×
×
×
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