參數(shù)資料
型號(hào)： EDE1108ABSE-6C-E
廠商： ELPIDA MEMORY INC
元件分類(lèi)： DRAM
英文描述： 1G bits DDR2 SDRAM
中文描述： 128M X 8 DDR DRAM, 0.45 ns, PBGA68
封裝： ROHS COMPLIANT, FBGA-68
文件頁(yè)數(shù)： 9/82頁(yè)
文件大?。?/td> 618K
代理商： EDE1108ABSE-6C-E
EDE1104ABSE, EDE1108ABSE, EDE1116ABSE
Data Sheet E0852E50 (Ver. 5.0)
9
max.
Parameter
Symbol
Grade
-8E
-6C
-6E
-5C
-4A
-8E
-6C
-6E
-5C
-4A
×
4
×
8
×
16
Unit
Test condition
tCK = tCK (IDD);
Refresh command at every tRFC (IDD) interval;
CKE is H, /CS is H between valid commands;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Self-Refresh Mode;
CK and /CK at 0V;
CKE
≤
0.2V;
Other control and address bus inputs are FLOATING;
Data bus inputs are FLOATING
all bank interleaving reads, IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = tRCD (IDD)
1
×
tCK (IDD);
tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD),
tFAW = tFAW (IDD), tRCD = 1
×
tCK (IDD);
CKE is H, CS is H between valid commands;
Address bus inputs are STABLE during DESELECTs;
Data pattern is same as IDD4W;
Auto-refresh current
IDD5
350
335
335
320
310
10
10
10
10
10
350
335
335
320
310
10
10
10
10
10
335
320
310
10
10
10
mA
Self-refresh current
IDD6*
7
mA
Operating current
(Bank interleaving)
IDD7
-8E
-6C
-6E
-5C
-4A
330
305
305
300
280
340
315
315
310
300
360
350
340
mA
Notes: 1. IDD specifications are tested after the device is properly initialized.
2. Input slew rate is specified by AC Input Test Condition.
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, /DQS, RDQS and /RDQS. IDD values must be met with all
combinations of EMRS bits 10 and 11.
5. Definitions for IDD
L is defined as VIN
≤
VIL (AC) (max.)
H is defined as VIN
≥
VIH (AC) (min.)
STABLE is defined as inputs stable at an H or L level
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as:
inputs changing between H and L every other clock cycle (once per two clocks) for address and control
signals, and inputs changing between H and L every other data transfer (once per clock) for DQ signals
not including masks or strobes.
6. Refer to AC Timing for IDD Test Conditions.
7. When TC
≥
+85
°
C, IDD6 must be derated by 80%.
IDD6 will increase by this amount (IDD6 will be 18mA), if TC
≥
+85
°
C and double refresh option is still
enabled.
相關(guān)PDF資料
PDF描述
EDE1108ABSE-6E-E 1G bits DDR2 SDRAM
EDE1108ABSE-8E-E 1G bits DDR2 SDRAM
EDE1116ABSE 1G bits DDR2 SDRAM
EDE1116ABSE-4A-E 1G bits DDR2 SDRAM
EDE1116ABSE-5C-E 1G bits DDR2 SDRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EDE1108ABSE-6E-E 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:1G bits DDR2 SDRAM
EDE1108ABSE-8E-E 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:1G bits DDR2 SDRAM
EDE1108ACBG 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:1G bits DDR2 SDRAM
EDE1108ACBG-5C-E 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:1G bits DDR2 SDRAM
EDE1108ACBG-6E-E 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:1G bits DDR2 SDRAM
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