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參數(shù)資料
| 型號(hào)： | EDI2CG272128V9D1 |
| 英文描述： | 2x128Kx72, 3.3V S nc/S nc Burst Flow-Through(2x128Kx72, 3.3V，9ns,同步/同步脈沖靜態(tài)RAM模塊(流通結(jié)構(gòu)）) |
| 中文描述： | 2x128Kx72，3.3VS數(shù)控/ s的數(shù)控突發(fā)流量通過(guò)（2x128Kx72，3.3伏，納秒，同步/同步脈沖靜態(tài)內(nèi)存模塊（流通結(jié)構(gòu)）） |
| 文件頁(yè)數(shù)： | 8/11頁(yè) |
| 文件大?。?/td> | 172K |
| 代理商： | EDI2CG272128V9D1 |
EDI2CG272128V
6
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
August 2000 Rev.0
ECO#13088
FIG. 3 SYNCHRONOUS ONLY READ CYCLE
READ CYCLE TIMING PARAMETERS
*TBD
8.5ns
9ns
12ns
15ns
Description
Sym
Min
Max
Min
Max
Min
Max
Min
Max
Units
Clock Cycle Time
tKHKH
**10
12
15
ns
Clock High Time
tKHKL
**
4
5
ns
Clock Low Time
tKLKH
**
4
5
ns
Clock to Output Valid
tKHQV
**
9
10
12
ns
Clock to Output Invalid
tKHQX1
**
3
ns
Clock to Output Low-Z
tKHQX
**
2
ns
Output Enable to Output Valid
tGLQV
**
4
5
ns
Output Enable to Output Low-Z
tGLQX
**
0
ns
Output Enable to Output High-Z
tGHQZ
**
4
5
ns
Address Setup
tAVKH
*
2.5
ns
Bank Enable Setup
tEVKH
*
2.5
ns
Address Hold
tKHAX
*
1.0
ns
Bank Enable Hold
tKHEX
*
1.0
ns
First
Second
Third
Fourth
Address
(external)
(internal)
A..A00
A..A01
A..A10
A..A11
A..A01
A..A00
A..A11
A..A10
A..A11
A..A00
A..A01
A..A11
A..A10
A..A01
A..A00
BURST ADDRESS TABLE (MODE = VSS)
BURST ADDRESS TABLE (MODE = NC/VCC)
First
Second
Third
Fourth
Address
(external)
(internal)
A..A00
A..A01
A..A10
A..A11
A..A01
A..A10
A..A11
A..A00
A..A10
A..A11
A..A00
A..A01
A..A11
A..A00
A..A01
A..A10
tKHQX
DQ
Read Cycle
Q(Addr 1)
Q(Addr 2)
tKHQZ
GW
G
ADDR
EX
CLK
tKHQV
Addr 1
Addr 2
Addr 1
tKHKH
tKLKH
tKHKL
tGLQX
Back to Back Read
tKHQX1
tGLQV
tKHAX
tAVKH
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EDI2CG27264V10D1 | 2x64Kx72, 3.3V,10ns, Sync/Sync Burst SRAM Module(2x64Kx72, 3.3V，10ns,同步/同步脈沖靜態(tài)RAM模塊) |
| EDI2CG27264V12D1 | 2x64Kx72, 3.3V,12ns, Sync/Sync Burst SRAM Module(2x64Kx72, 3.3V，12ns,同步/同步脈沖靜態(tài)RAM模塊) |
| EDI2CG27264V85D1 | 2x64Kx72, 3.3V,8.5ns, Sync/Sync Burst SRAM Module(2x64Kx72, 3.3V，8.5ns,同步/同步脈沖靜態(tài)RAM模塊) |
| EDI2CG27264V9D1 | 2x64Kx72, 3.3V,9ns, Sync/Sync Burst SRAM Module(2x64Kx72, 3.3V，9ns,同步/同步脈沖靜態(tài)RAM模塊) |
| EDI2CG472128V10D2 | 4x128Kx72, 3.3V Sync/Sync Burst SRAM(4x128Kx72, 3.3V，10ns,同步/同步脈沖靜態(tài)RAM模塊) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EDI2CG272128V-D1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SSRAM Modules |
| EDI2CG472128V | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:4 Megabyte Sync/Sync Burst, Dual Key DIMM |
| EDI2CG472128V10D2 | 制造商:EDI 功能描述: |
| EDI2CG472128V12D2 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:4 Megabyte Sync/Sync Burst, Dual Key DIMM |
| EDI2CG472128V15D2 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:4 Megabyte Sync/Sync Burst, Dual Key DIMM |
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