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參數資料
| 型號： | EDI2CG27264V10D1 |
| 英文描述： | 2x64Kx72, 3.3V,10ns, Sync/Sync Burst SRAM Module(2x64Kx72, 3.3V，10ns,同步/同步脈沖靜態(tài)RAM模塊) |
| 中文描述： | 2x64Kx72，3.3伏，10納秒，同步/同步突發(fā)靜態(tài)存儲器模塊（2x64Kx72，3.3伏，10納秒，同步/同步脈沖靜態(tài)內存模塊） |
| 文件頁數： | 6/11頁 |
| 文件大?。?/td> | 2510K |
| 代理商： | EDI2CG27264V10D1 |
4
White Electronic Designs Corporation Westborough, MA 01581
(508) 366-5151 www.whiteedc.com
EDI2CG27264V
July 1999 Rev
ECO
PIN DESCRIPTIONS
DIMM Pins
Symbol
Type
Description
3, 6, 7, 10, 11, 14, A0-A15
Input
Addresses: These inputs are registered and must meet the setup and hold
15, 18, 19, 20, 17,
Synchronous times around the rising edge of CLK. The burst counter generates internal
16, 13, 12, 9, 8, 3
addresses associated with A0 and A1, during burst and wait cycle.
25
GW\
Input
Global Write: This active LOW input allows a full 72-bit WRITE to occur
Synchronous
independent of the BWE\ and BWx\ lines and must meet the setup and hold
times around the rising edge of CLK.
30
CLK
Input
Clock: This signal registers the addresses, data, chip enables, write control
Synchronous
and burst control inputs on its rising edge. All synchronous inputs must
meet setup and hold times around the clock’s rising edge.
33,61
E1\, E2\
Input
Bank Enables: These active LOW inputs are used to enable each
Synchronous
individual bank and to gate ADSP\.
23
G\
Input
Output Enable: This active LOW asynchronous input enables the data output
drivers.
26
ADV\
Input
Address Status Processor: This active LOW input is used to control the
Synchronous
internal burst counter. A HIGH on this pin generates wait cycle (no address
advance).
27
ADSP\
Input
Address Status Processor: This active LOW input, along with EL\ and EH\
Synchronous
being LOW, causes a new external address to be registered and a READ
cycle is initiated using the new address.
28
ADSC\
Input
Address Status Controller: This active LOW input causes device to be de-
Synchronous
selected or selected along with new external address to be registered. A
READ or WRITE cycle is initiated depending upon write control inputs.
29
MODE
InputStatic
Mode: This input selects the burst sequence. A LOW on this pin selects
LINEAR BURST. A NC or HIGH on this pin selects INTERLEAVED
BURST.
47,75
ZZ1,ZZ2,
Input
Snooze: These active HIGH inputs put the individual banks in low power
Asynchronous consumption standby mode. For normal operation, this input
has to be either LOW or NC (no connect).
Various
DQ0-63
Input/Output
Data Inputs/Outputs: First byte is DQ0-7, second byte is DQ8-15, third byte is
DQ16-23, fourth byte is DQ24-31, fifth byte is DQ32-39, sixth byte is
DQ40-47, seventh byte is DQ48-55 and the eight byte is DQ56-64.
34, 48, 62, 76,
DQP0-7
Input/Output
Parity Inputs/Outputs: DQP0 is parity bit for DQ0-7. DQP1 is parity bit for
DQ8-15.
90, 104, 118,132
DQP2 is parity bit for DQ16-23. DQP3 is parity bit for DQ24-31. DQP4\ is
parity bit for DQ32-39. DQP5 is parity bit for DQ40-47. DQP6\ is parity bit for
DQ48-55. DQP7 is parity bit for DQ56-64 and DQP7. In order to use the device
configured as a 128K x 64, the parity bits need to be tied to Vss through a 10K
ohm resistor..
Various
Vcc
Supply
Corepowersupply:+3.3V-5%/+10%
Various
Vss
Ground
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相關代理商/技術參數 |
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| EDI2CG472128V | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:4 Megabyte Sync/Sync Burst, Dual Key DIMM |
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