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參數(shù)資料
| 型號(hào)： | EDI2CG472128V15D2 |
| 英文描述： | 4x128Kx72, 3.3V Sync/Sync Burst SRAM(4x128Kx72, 3.3V，15ns,同步/同步脈沖靜態(tài)RAM模塊) |
| 中文描述： | 4x128Kx72，3.3同步/同步突發(fā)靜態(tài)存儲(chǔ)器（4x128Kx72，3.3伏，15納秒，同步/同步脈沖靜態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 354K |
| 代理商： | EDI2CG472128V15D2 |
EDI2CG472128V
4
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
PIN DESCRIPTIONS
DIMM Pins
Symbol
Type
Description
2, 87, 4, 89, 7, 92
A0-16
Input
Addresses: These inputs are registered and must meet the setup and hold times around the rising edge of CLK. The
9, 94, 12, 96, 10
Synchronous
burst counter generates internal addresses associated with A0 and A1, during burst and wait cycle.
93, 8, 91, 5, 88, 3
107, 106, 23,
BW1\, BW1\,
Input
Byte Write: A byte write is LOW for a WRITE cycle and HIGH for a READ cycle. BW0/ controls DQ0-7 and DQP0, BW1\
22, 109, 108,
BW3\, BW4\,
Synchronous
controls DQ8-15 and DQP1. BW2\ controls DQ16-23 and DQP2. BW3\ controls DQ24-31 and DQP3. BW4\ controls DQ32-39
25, 24
BW5\, BW6\,
and DQP4. BW5\ controls DQ40-47 and DQP5. BW6\ controls DQ48-55 and DQP6. BW7\ controls DQ56-64 and DQP7.
BW7\, BW8\
104
BWE\
Input
Write Enable: This active LOW input gates byte write operations and must meet the setup and hold times around the
Synchronous
rising edge of CLK.
19
GW\
Input
Global Write: This active LOW input allows a full 72-bit WRITE to occur independent of the BWE\ and BWx\ lines and
Synchronous
must meet the setup and hold times around the rising edge of CLK.
101
CLK
Input
Clock: This signal registers the addresses, data, chip enables, write control and burst control inputs on its rising edge.
Synchronous
All synchronous inputs must meet setup and hold times around the clock’s rising edge.
98, 15,
E1\, E2\
Input
Bank Enables: These active LOW inputs are used to enable each individual bank and to gate ADSP\.
99,14
E3\, E4\
Synchronous
103
G\
Input
Output Enable: This active LOW asynchronous input enables the data output drivers.
111
ADV\
Input
Address Status Processor: This active LOW input is used to control the internal burst counter. A HIGH on this pin
Synchronous
generates wait cycle (no address advance).
27
ADSP\
Input
Address Status Processor: This active LOW input, along with EL\ and EH\ being LOW, causes a new external
Synchronous
address to be registered and a READ cycle is initiated using the new address.
26
ADSC\
Input
Address Status Controller: This active LOW input causes device to be de-selected or selected along with new
Synchronous
external address to be registered. A READ or WRITE cycle is initiated depending upon write control inputs.
17
MODE
Input Static
Mode: This input selects the burst sequence. A LOW on this pin selects LINEAR BURST. A NC or HIGH on this pin
selects INTERLEAVED BURST.
36, 50,
ZZ1, ZZ2,
Input
Snooze: These active HIGH inputs put the individual banks in low power consumption standby mode.
64, 78
ZZ3, ZZ4
Asynchronous
For normal operation, this input has to be either LOW or NC (no connect).
Various
DQ0-63
Input/Output
Data Inputs/Outputs: First byte is DQ0-7, second byte is DQ8-15, third byte is DQ16-23, fourth byte is DQ24-31, fifth byte is
DQ32-39, sixth byte is DQ40-47, seventh byte is DQ48-55 and the eight byte is DQ56-64.
113, 120, 127,
DQP0-7
Input/Output
Parity Inputs/Outputs: DQP0 is parity bit for DQ0-7. DQP1 is parity bit for DQ8-15. DQP2 is parity bit for DQ16-23. DQP3
134, 141, 148,
is parity bit for DQ24-31. DQP4\ is parity bit for DQ32-39. DQP5 is parity bit for DQ40-47. DQP6\ is parity bit for DQ48-55.
155, 162
DQP7 is parity bit for DQ56-64 and DQP7. In order to use the device configured as a 128K x 64, the parity bits need to
be tied to Vss through a 10K ohm resistor.
Various
Vcc
Supply
Core power supply: +3.3V -5%/+10%
Various
Vss
Ground
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EDI2CG472128V85D2 | 4x128Kx72, 3.3V Sync/Sync Burst SRAM(4x128Kx72, 3.3V，8.5ns,同步/同步脈沖靜態(tài)RAM模塊) |
| EDI2CG472256V10D2 | 4x256Kx72, 3.3V Synchronous/Synchronous Burst Flow-Through(4x256Kx72, 3.3V，10ns,同步/同步脈沖靜態(tài)RAM模塊(流通結(jié)構(gòu)）) |
| EDI2CG472256V12D2 | 4x256Kx72, 3.3V Synchronous/Synchronous Burst Flow-Through(4x256Kx72, 3.3V，12ns,同步/同步脈沖靜態(tài)RAM模塊(流通結(jié)構(gòu)）) |
| EDI2CG472256V15D2 | 4x256Kx72, 3.3V Synchronous/Synchronous Burst Flow-Through(4x256Kx72, 3.3V，15ns,同步/同步脈沖靜態(tài)RAM模塊(流通結(jié)構(gòu)）) |
| EDI2CG472256V9D2 | 4x256Kx72, 3.3V Synchronous/Synchronous Burst Flow-Through(4x256Kx72, 3.3V，9ns,同步/同步脈沖靜態(tài)RAM模塊(流通結(jié)構(gòu)）) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EDI2CG472128V85D2 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:4 Megabyte Sync/Sync Burst, Dual Key DIMM |
| EDI2CG472128V-D2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SSRAM Modules |
| EDI2CG472256V | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8 Megabyte Sync/Sync Burst, Dual Key DIMM |
| EDI2CG472256V10D2 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8 Megabyte Sync/Sync Burst, Dual Key DIMM |
| EDI2CG472256V12D2 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8 Megabyte Sync/Sync Burst, Dual Key DIMM |
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