參數(shù)資料
型號(hào): EDI2KG46464V11D
英文描述: 4x64Kx64, 3.3V Synchronous Flow-Through Card Module(4x64Kx64, 3.3V,11ns,同步靜態(tài)RAM卡模塊(流通結(jié)構(gòu)))
中文描述: 4x64Kx64,3.3V的同步流動(dòng),通過(guò)卡模塊(4x64Kx64,3.3伏,11ns,同步靜態(tài)內(nèi)存卡模塊(流通結(jié)構(gòu)))
文件頁(yè)數(shù): 5/8頁(yè)
文件大?。?/td> 126K
代理商: EDI2KG46464V11D
EDI2KG46464V
2 Megabyte Synchronous
Card Edge DIMM
5
EDI2KG46464V Rev. 0 4/98 ECO#9976
Max
Description
SYM
Typ
9.5
10
11
12
15
Units
Power Supply Current
Icc1
1.8
*
1.2
1.1
1.0
.9
A
Power Supply Current
Icc
.8
*
.9
.8
.7
A
Device Selected,No Operation
Snooze Mode
IccZZ
500
*
700 700 700 700
mA
CMOS Standby
Icc3
270
*
350 350 350 350
mA
Clock Running-Deselect IccK
900
*
1.1
1.0
A
DC Electrical Characteristics - Read Cycle
Parameter
Sym
Min
Typ
Max
Units
Supply Voltage
VCC 3.14
3.3
3.6
V
Supply Voltage
VSS
0.0
V
Input High
VIH
1.1
3.0
VCC+0.3 V
Input Low
VIL
-0.3
0.0
0.3
V
Input Leakage
ILi
-2
1
2
A
Output Leakage
ILo
-2
1
2
A
Recommended DC Operating Conditions
AC Test Conditions
Input Pulse Levels
Vss to 3.0V
Input and Output Timing Ref.
1.25V
Output Test equivalencies
AC Test Load
DQ
Z
0 = 50 W
F ig . 1 O u tput L o ad Equiva lent
V t = 1.25V
50
W
*TBD
9.5ns
10ns
11ns
12ns
15ns
Description
Sym
Min Max
Min
Max
Units
Clock Cycle Time
tKhKh
*
12
13
15
20
ns
Clock High Time
tKHKL
*
5
6
ns
Clock Low Time
tKLKH
*
5
6
ns
Clock to Output Valid
tKHQV
*
10
11
12
15
ns
Clock to Output Invalid
tKHQX1
*
3
ns
Clock to Output Low-Z
tKHQX
*
2
4
Output Enable to Output Valid
tGLQV
*
4
5
6
ns
Output Enable to Output Low-Z
tGLQX
*
0
ns
Output Enable to Output High-Z
tGHQZ
*
4
5
6
ns
Address Setup
tAVKH
*
2.5
ns
Bank Enable Setup
tEVKH
*
2.5
ns
Address Hold
tKHAX
*
1.0
ns
Bank Enable Hold
tKHEX
*
1.0
ns
Read Cycle Timing Parameters
*TBD
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