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參數(shù)資料
| 型號(hào)： | EDI88512CA20F36C |
| 英文描述： | 2.5MHz 4, 8, 10 & 12 Channel Rail-to-Rail Buffers; Temperature Range: -40°C to 85°C; Package: 24-QFN T&R |
| 中文描述： | x8的SRAM |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 152K |
| 代理商： | EDI88512CA20F36C |
1
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
HI-RELIABILITY PRODUCT
EDI88128C
128Kx8 Monolithic SRAM, SMD 5962-89598
FEATURES
s Access Times of 70, 85, 100ns
s Available with Single Chip Selects (EDI88128) or Dual Chip
Selects (EDI88130)
s 2V Data Retention (LP Versions)
s CS and OE Functions for Bus Control
s TTL Compatible Inputs and Outputs
s Fully Static, No Clocks
s Organized as 128Kx8
s Industrial, Military and Commercial Temperature Ranges
s Thru-hole and Surface Mount Packages JEDEC Pinout
32 pin Ceramic DIP, 0.6 mils wide (Package 9)
32 lead Ceramic ZIP (Package 100)
32 lead Ceramic SOJ (Package 140)
s Single +5V (
±10%) Supply Operation
32 ZIP
TOP VIEW
July 1999 Rev. 13
PIN DESCRIPTION
I/O0-7
Data Inputs/Outputs
A0-16
Address Inputs
WE
Write Enable
CS1, CS2
Chip Selects
OE
Output Enable
VCC
Power (+5V
±10%)
VSS
Ground
NC
Not Connected
BLOCK DIAGRAM
Memory Array
Address
Buffer
Address
Decoder
I/O
Circuits
A-16
I/O-7
WE
CS1
CS2
OE
FIG. 1
PIN CONFIGURATION
The EDI88128C is a high speed, high performance, Monolithic
CMOS Static RAM organized as 128Kx8.
The device is also available as EDI88130C with an additional chip
select line (CS2) which will automatically power down the device
when proper logic levels are applied.
The second chip select line (CS2) can be used to provide system
memory security during power down in non-battery backed up
systems and simplifiy decoding schemes in memory banking
where large multiple pages of memory are required.
The EDI88128C and the EDI88130C have eight bi-directional in-
put-output lines to provide simultaneous access to all bits in a
word. An automatic power down feature permits the on-chip
circuitry to enter a very low standby mode and be brought back
into operation at a speed equal to the address access time.
Low power versions, EDI88128LP and EDI88130LP, offer a 2V data
retention function for battery back-up opperation. Military prod-
uct is available compliant to Appendix A of MIL-PRF-38535.
32 DIP
32 SOJ
TOP VIEW
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
VCC
A15
NC/CS2*
WE
A13
A8
A9
A11
OE
A10
CS1
I/O7
I/O6
I/O5
I/O4
I/O3
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A
I/O
I/O1
I/O2
VSS
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VCC
A15
NC/CS2*
WE
A13
A8
A9
A11
OE
A10
CS1
I/O7
I/O6
I/O5
I/O4
I/O3
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A
I/O
I/O1
I/O2
VSS
* Pin 30 is NC for 88128 or CS2 for 88130.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EDI88512CA20F36I | 2.5MHz 4, 8, 10 & 12 Channel Rail-to-Rail Buffers; Temperature Range: -40°C to 85°C; Package: 24-QFN T&R |
| EDI88512CA20F36M | 2.5MHz 4, 8, 10 & 12 Channel Rail-to-Rail Buffers; Temperature Range: -40°C to 85°C; Package: 20-TSSOP |
| EDI88512CA20KB | 2.5MHz 4, 8, 10 & 12 Channel Rail-to-Rail Buffers; Temperature Range: -40°C to 85°C; Package: 20-TSSOP T&R |
| EDI88512CA20KC | 2.5MHz 4, 8, 10 & 12 Channel Rail-to-Rail Buffers; Temperature Range: -40°C to 85°C; Package: 20-TSSOP T&R |
| EDI88512CA20KI | 2.5MHz 4, 8, 10 & 12 Channel Rail-to-Rail Buffers; Temperature Range: -40°C to 85°C; Package: 20-TSSOP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EDI88512CA20F36I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| EDI88512CA20F36M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| EDI88512CA20KB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| EDI88512CA20KC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| EDI88512CA20KI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
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