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參數(shù)資料
| 型號： | EDI88512VA25MM |
| 英文描述： | 12MHz 4-, 8-, 10- and 12-Channel Rail-to-Rail Input-Output Buffers; Temperature Range: -40°C to 85°C; Package: 32-QFN T&R |
| 中文描述： | x8的SRAM |
| 文件頁數(shù)： | 3/8頁 |
| 文件大?。?/td> | 152K |
| 代理商： | EDI88512VA25MM |
3
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
EDI88128C
Input Pulse Levels
VSS to 3.0V
Input Rise and Fall Times
5ns
Input and Output Timing Levels
1.5V
Output Load
Figure 1
NOTE: For tEHQZ, tGHQZ and tWLQZ, CL = 5pF Figure 2)
30pF
480
Vcc
Q
Figure 1
Figure 2
255
5pF
480
Vcc
Q
255
AC TEST CONDITIONS
AC CHARACTERISTICS – READ CYCLE
(VCC = 5.0V, VSS = 0V, TA = 0
°C to +70°C)
Symbol
70ns
85ns
100ns
Parameter
JEDEC
Alt.
Min
Max
Min
Max
Min
Max
Units
Read Cycle Time
tAVAV
tRC
70
85
100
ns
Address Access Time
tAVQV
tAA
70
85
100
ns
Chip Select Access Time
tELQV
tACS
70
85
100
ns
tSHQV
tACS
70
85
100
ns
Chip Select to Output in Low Z (1)
tELQX
tCLZ
33
3
ns
tSHQX
tCLZ
33
3
ns
Chip Disable to Output in High Z (1)
tEHQZ
tCHZ
030
0
30
030
ns
tSLQZ
tCHZ
030
0
30
030
ns
Output Hold from Address Change
tAVQX
tOH
33
3
ns
Output Enable to Output Valid
tGLQV
tOE
25
30
50
ns
Output Enable to Output in Low Z (1)
tGLQX
tOLZ
00
0
ns
Output Disable to Output in High Z (1)
tGHQZ
tOHZ
030
0
30
030
ns
1. This parameter is guaranteed by design but not tested.
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