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參數(shù)資料
| 型號： | EDI8L24129V |
| 英文描述： | 128Kx24 SRAM 3.3 Volt(128Kx24, 3.3V,CMOS靜態(tài)RAM) |
| 中文描述： | 128Kx24 SRAM的3.3伏（128Kx24，3.3伏，靜態(tài)內(nèi)存的CMOS） |
| 文件頁數(shù)： | 8/8頁 |
| 文件大?。?/td> | 512K |
| 代理商： | EDI8L24129V |
8
White Electronic Designs Corporation Westborough, MA 01581
(508) 366-5151 www.whiteedc.com
EDI8L24129V
July1999 Rev
ECO
FIGURE 3 - INTERFACING THE MOTOROLA DSP5630X DSP FAMILY WITH THE
EDI8L24129V (128KX24).
Interfacing the Motorola DSP5630x DSP Family with the EDI8L24129V (128K x 24)
Motorola
DSP5630x
Address Bus
A23 - A0
Databus
D23 - D0
EDI8L24129V
DQ0-DQ23
A16 - A0
E\
W\
G\
EDI8L24129V
(128K x 24)
A16 - A0
E\
W\
G\
A16 - A0
E\
W\
G\
AA0
AA1
AA2
AA3
WR/
RD/
DQ0-DQ23
Notes:
1) In this example three 128K x 24 external memory arrays are
shown, one for X data, one for Y data and one for Program.
Specific applications may require one, two or all three arrays.
2)Any combination of AA0-AA3 may be used as chip selects.
However, each chip select may only be used to select one
memory array.
EDI8L24129V
(128K x 24)
A16-A0
E\
W\
G\
DQ16-23
DQ8-15
DQ0-7
EDI8L24129V
(128K x 24)
A16-A0
E\
W\
G\
DQ16-23
DQ8-15
DQ0-7
Analog
ADSP-2106XL
Address bus
A31-A0
MSx\
WR\
RD\
Data Bus
D47-D0
(creating a 128K x 48 memory Array)
FIGURE 4 - INTERFACING THE 21060L OR THE 21062L TO THE EDI8L24129V, 119 BGA
(CREATING A 128KX48
MEMORY ARRAY.
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