參數(shù)資料
型號： EFM32TG230F32
廠商： Energy Micro
文件頁數(shù)： 88/136頁
文件大小： 0K
描述： MCU 32BIT 32KB FLASH 64-QFN
特色產(chǎn)品： EFM32 Tiny Gecko
標準包裝： 1
系列： Tiny Gecko
核心處理器： ARM? Cortex?-M3
芯體尺寸： 32-位
速度： 32MHz
連通性： EBI/EMI，I²C，IrDA，智能卡，SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，DMA，POR，PWM，WDT
輸入/輸出數(shù)： 56
程序存儲器容量： 32KB（32K x 8）
程序存儲器類型： 閃存
RAM 容量： 4K x 8
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 3.8 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x12b，D/A 2x12b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 64-VFQFN 裸露焊盤
包裝： 標準包裝
其它名稱： 914-1035-6
...the world's most energy friendly microcontrollers
2011-02-04 - d0002_Rev1.00
55
www.energymicro.com
STREXH{cond} Rd, Rt, [Rn]
where:
cond
is an optional condition code, see Section 3.3.7 (p. 43) .
Rd
is the destination register for the returned status.
Rt
is the register to load or store.
Rn
is the register on which the memory address is based.
offset
is an optional offset applied to the value in Rn. If offset is omitted, the address is the value
in Rn.
3.4.8.2 Operation
LDREX
, LDREXB, and LDREXH load a word, byte, and halfword respectively from a memory address.
STREX
, STREXB, and STREXH attempt to store a word, byte, and halfword respectively to a memory
address. The address used in any Store-Exclusive instruction must be the same as the address in the
most recently executed Load-exclusive instruction. The value stored by the Store-Exclusive instruction
must also have the same data size as the value loaded by the preceding Load-exclusive instruction.
This means software must always use a Load-exclusive instruction and a matching Store-Exclusive
instruction to perform a synchronization operation, see Section 2.2.7 (p. 20)
If an Store-Exclusive instruction performs the store, it writes 0 to its destination register. If it does not
perform the store, it writes 1 to its destination register. If the Store-Exclusive instruction writes 0 to the
destination register, it is guaranteed that no other process in the system has accessed the memory
location between the Load-exclusive and Store-Exclusive instructions.
For reasons of performance, keep the number of instructions between corresponding Load-Exclusive
and Store-Exclusive instruction to a minimum.
Note
The result of executing a Store-Exclusive instruction to an address that is different from that
used in the preceding Load-Exclusive instruction is unpredictable.
3.4.8.3 Restrictions
In these instructions:
do not use PC
do not use SP for Rd and Rt
for STREX, Rd must be different from both Rt and Rn
the value of offset must be a multiple of four in the range 0-1020.
3.4.8.4 Condition flags
These instructions do not change the flags.
3.4.8.5 Examples
MOV
R1, #0x1
; Initialize the ‘lock taken’ value
try
LDREX
R0, [LockAddr]
; Load the lock value
CMP
R0, #0
; Is the lock free?
ITT
EQ
; IT instruction for STREXEQ and CMPEQ
STREXEQ R0, R1, [LockAddr]
; Try and claim the lock
CMPEQ
R0, #0
; Did this succeed?
BNE
try
; No – try again
....
; Yes – we have the lock
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