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參數(shù)資料
| 型號(hào)： | EL2141CSZ |
| 廠商： | Intersil |
| 文件頁(yè)數(shù)： | 4/6頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DIFF PAIR DRIVER 8-SOIC |
| 標(biāo)準(zhǔn)包裝： | 97 |
| 放大器類型： | 差分 |
| 電路數(shù)： | 1 |
| 輸出類型： | 差分 |
| 轉(zhuǎn)換速率： | 800 V/µs |
| 增益帶寬積： | 400MHz |
| -3db帶寬： | 150MHz |
| 電流 - 輸入偏壓： | 6µA |
| 電壓 - 輸入偏移： | 10000µV |
| 電流 - 電源： | 11mA |
| 電流 - 輸出 / 通道： | 60mA |
| 電壓 - 電源，單路/雙路(±)： | 6 V ~ 12.6 V，±3 V ~ 6.3 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 管件 |
4
FN7048.1
February 11, 2005
Applications Information
Choice of Feedback Resistor
There is little to be gained from choosing resistor R2 values
below 400
Ω and, in fact, it would only result in increased
power dissipation and signal distortion. Above 400
Ω, the
bandwidth response will develop some peaking (for a gain of
two), but substantially higher resistor R2 values may be used
for higher voltage gains, such as up to 2k
Ω at a gain of eight
before peaking will develop. R1 and R3 are selected as
needed to set the voltage gain, and while R1 = R3 is sug-
gested, the gain equation above holds for any values (see
distortion for further suggestions).
Capacitance Considerations
As with many high bandwidth amplifiers, the EL2141 prefers
not to drive highly capacitive loads. It is best if the capaci-
tance on VOUT and VOUTB is kept below 10pF if the user
does not want gain peaking to develop.
In addition, on the EL2141, the two feedback nodes FBP and
FBN should be laid out so as to minimize stray capacitance,
else an additional pole will potentially develop in the
response with possible gain peaking.
The amount of capacitance tolerated on any of these nodes
in an actual application will also be dependent on the gain
setting and the resistor values in the feedback network.
Distortion Considerations
The harmonics that these amplifiers will potentially produce
are the 2nd, 3rd, 5th, and 6th. Their amplitude is application
dependent. All other harmonics should be negligible by com-
parison. Each should be considered separately:
H2 The second harmonic arises from the input stage, and
the lower the applied differential signal amplitude, the lower
the magnitude of the second harmonic. For practical consid-
erations of required output signal and input noise levels, the
user will end up choosing a circuit gain. Referring to Figure 1,
it is best if the voltage at the negative feedback node tracks
the VREF node, and the voltage at the positive feedback
node tracks the VIN node respectively. This would theoreti-
cally require that R1 + R2 = R3, although the lowest
distortion is found at about R3 = R1 + (0.7*R2). With this
arrangement, the second harmonic should be suppressed
well below the value of the third harmonic.
H3 The third harmonic should be the dominant harmonic and
is primarily affected by output load current which, of course,
is unavoidable. However, this should encourage the user not
to waste current in the gain setting resistors, and to use val-
ues that consume only a small proportion of the load current,
so long as peaking does not occur. The more load current,
the worse the distortion, but depending on the frequency, it
may be possible to reduce the amplifier gain so that there is
more internal gain left to cancel out any distortion.
H5 The fifth harmonic should always be below the third, and
will not become significant until heavy load currents are
drawn. Generally, it should respond to the same efforts
applied to reducing the third harmonic.
H6 The sixth harmonic should not be a problem and is the
result of poor power supply decoupling. While 100nF chip
capacitors may be sufficient for some applications, it would
be insufficient for driving full signal swings into a twisted pair
line at 100kHz. Under these conditions, the addition of 4.7
μF
tantalum capacitors would cure the problem.
FIGURE 5. DISTORTION vs FREQUENCY
(GAIN = 6, RLOAD = 200Ω) VIN = 2VPK-PK
FIGURE 6. OUTPUT SIGNAL AND COMMON MODE SIGNAL
vs FREQUENCY
Typical Performance Curves (Continued)
GAIN
R1 R2 R3
++
R2
-------------------------------------
=
EL2141
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EL2141CSZT13 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:150MHz Differential Twisted Pair Driver |
| EL2141CSZ-T13 | 功能描述:IC DRVR TWISTED PR 150MHZ 8-SOIC RoHS:是 類別:集成電路 (IC) >> Linear - Amplifiers - Instrumentation 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 放大器類型:通用 電路數(shù):4 輸出類型:滿擺幅 轉(zhuǎn)換速率:0.6 V/µs 增益帶寬積:1MHz -3db帶寬:- 電流 - 輸入偏壓:2pA 電壓 - 輸入偏移:1000µV 電流 - 電源:85µA 電流 - 輸出 / 通道:20mA 電壓 - 電源，單路/雙路(±):1.8 V ~ 6 V 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:14-SOICN 包裝:剪切帶 (CT) 產(chǎn)品目錄頁(yè)面:680 (CN2011-ZH PDF) 其它名稱:MCP6L04T-E/SLCT |
| EL2141CSZ-T7 | 功能描述:IC DRVR TWISTED PR 150MHZ 8-SOIC RoHS:是 類別:集成電路 (IC) >> Linear - Amplifiers - Instrumentation 系列:- 標(biāo)準(zhǔn)包裝:50 系列:- 放大器類型:通用 電路數(shù):2 輸出類型:滿擺幅 轉(zhuǎn)換速率:1.8 V/µs 增益帶寬積:6.5MHz -3db帶寬:4.5MHz 電流 - 輸入偏壓:5nA 電壓 - 輸入偏移:100µV 電流 - 電源:65µA 電流 - 輸出 / 通道:35mA 電壓 - 電源，單路/雙路(±):1.8 V ~ 5.25 V，±0.9 V ~ 2.625 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:10-TFSOP，10-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:10-MSOP 包裝:管件 |
| EL2142 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Differential Line Receiver |
| EL2142C | 制造商:ELANTEC 制造商全稱:ELANTEC 功能描述:Differential Line Receiver |
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