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參數(shù)資料
| 型號： | EL4585CS |
| 廠商： | Intersil |
| 文件頁數(shù)： | 3/15頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL VIDEO GP 36MHZ 16-SOIC |
| 標準包裝： | 47 |
| 類型： | 鎖相環(huán)路（PLL） |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | CMOS，TTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 3:1 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 36MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 5V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC |
| 包裝： | 管件 |
11
FN7175.4
September 3, 2009
.
PCB Layout Considerations
It is highly recommended that power and ground planes be
used in layout. The oscillator and filter sections constitute a
feedback loop and thus care must be taken to avoid any
feedback signal influencing the oscillator except at the
control input. The entire oscillator/filter section should be
surrounded by copper ground to prevent unwanted
influences from nearby signals. Use separate paths for
analog and digital supplies, keeping the analog (oscillator
section) as short and free from spurious signals as possible.
Careful attention must be paid to correct bypassing. Keep
lead lengths short and place bypass caps as close to the
supply pins as possible. If laying out a PCB to use discrete
components for the VCO section, care must be taken to
avoid parasitic capacitance at the OSC pins 3 and 5, and
FILTER out (pin 7). Remove ground and power plane copper
above and below these traces to avoid making a capacitive
connection to them. It is also recommended to enclose the
oscillator section within a shielded cage to reduce external
influences on the VCO, as they tend to be very sensitive to
“hand waving” influences, the LC variety being more
sensitive than crystal controlled oscillators. In general, the
higher the operating frequency, the more important these
considerations are. Self contained VCXO or VCO modules
are already mounted in a shielding cage and therefore do
not require as much consideration in layout. Many crystal
manufacturers publish informative literature regarding use
and layout of oscillators which should be helpful.
LC LOOP FILTER COMPONENTS (APPROXIMATE)
FREQUENCY
(MHz)
R2
(k
Ω)
R3
(k
Ω)
C3
(F)
C4
(F)
26.602
100
39
0.01
0.001
27.0
100
39
0.01
0.001
29.5
100
43
0.01
0.001
35.468
100
51
0.01
0.001
21.476
100
30
0.01
0.001
24.546
100
36
0.01
0.001
28.636
100
43
0.01
0.001
FIGURE 12.
TYPICAL LOOP FILTER
XTAL LOOP FILTER COMPONENTS (APPROXIMATE)
FREQUENCY
(MHz)
R2
(k
Ω)
R3
(M
Ω)
C3
(pF)
C4
(pF)
26.602
100
4.3
68
6.8
27.0
100
4.3
68
6.8
29.5
100
4.3
68
6.8
35.468
100
4.3
68
6.8
21.476
100
4.3
68
6.8
24.546
100
4.3
68
6.8
28.636
100
4.3
68
6.8
EL4585
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| EL4585CS-T13 | 功能描述:IC GENLOCK HORZ 8FSC 16-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| EL4585CS-T7 | 功能描述:IC PLL VIDEO GP 36MHZ 16-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| EL4585CSZ | 功能描述:鎖相環(huán) - PLL EL4585CSZ HORIZONTAL GENLOCK RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| EL4585CSZ-T13 | 功能描述:鎖相環(huán) - PLL EL4585CSZ HORIZONTAL GENLOCK RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| EL4585CSZ-T7 | 功能描述:鎖相環(huán) - PLL EL4585CSZ HORIZONTAL GENLOCK RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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