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參數(shù)資料
| 型號： | EL4585CSZ-T7 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 13/15頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC GENLOCK HORZ 8FSC 16-SOIC |
| 標準包裝： | 1,000 |
| 類型： | 鎖相環(huán)路（PLL） |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | CMOS，TTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 3:1 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 36MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 5V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 16-SOIC |
| 包裝： | 帶卷 (TR) |
7
FN7175.4
September 3, 2009
EL4585 Block Diagram
Description Of Operation
The horizontal sync signal (CMOS level, falling leading edge)
is input to HSYNC input (pin 10). This signal is delayed about
200ns, the falling edge of which becomes the reference to
which the clock output will be locked (See “Timing Diagrams”
on page 5). The clock is generated by the signal on pin 5,
OSC IN. There are 2 general types of VCO that can be used
with the EL4585, LC and crystal controlled. Additionally,
each type can be either built up using discrete components,
including a varactor as the frequency controlling element, or
complete, self contained modules can be purchased with
everything inside a metal can. These modules are very
forgiving of PCB layout, but cost more than discrete
solutions. The VCO or VCXO is used to regulate the clock.
An LC tank resonator has greater “pull” than a crystal
controlled circuit, but will also be more likely to drift over
time, and thus will generate more jitter. The “pullability” of the
circuit refers to the ability to pull the frequency of oscillation
away from its center frequency by modulating the voltage on
the control pin of the VCO module or varactor, and is a
function of the slope and range of the capacitance-voltage
curve of the varactor or VCO module used. The VCO signal
is sent to the CLK out pin, divided by two, then sent to the
divide by N counter. The divisor N is determined by the state
of pins 1, 2, and 16 and is described in Table 1. The divided
signal is sent, along with the delayed HSYNC input, to the
phase/frequency detector, which compares the two signals
for phase and frequency differences. Any phase difference is
converted to a current at the charge pump output, (pin 7). A
VCO with a positive frequency deviation with control voltage
must be used. Varactors have negative capacitance slope
with voltage, resulting in positive frequency deviation with
increasing control voltage for the oscillators in Figures 10
and 11.
VCO
The VCO should be tuned so that its frequency of oscillation
is very close to the required clock output frequency when the
voltage on the varactor is 2.5V. VCXO and VCO modules are
already tuned to the desired frequency, so this step is not
necessary if using one of these units. The output range of
the charge pump output (pin 7) is 0V to 5V, and it can source
or sink a maximum of about 300A, so all frequency control
must be accomplished with variable capacitance from the
FIGURE 6. POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 7. POWER DISSIPATION vs AMBIENT
TEMPERATURE
Typical Performance Curves (Continued)
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
255075
100
125
150
AMBIENT TEMPERATURE (°C)
POW
E
R
D
ISSIP
A
TION
(
W
)
85
1.23W
0.91W
PDIP16
θJA = +81°C/W
SO16 (0.150”)
θJA = +110°C/W
1.43W
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.4
0.2
0
P
O
WE
R
DISS
IP
ATIO
N
(W
)
0.6
0
25
50
75
100
125
150
AMBIENT TEMPERATURE (°C)
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1.25W
PDIP16
θJA = +70°C/W
SO16 (0.150”)
θJA = +80°C/W
EL4585
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