12 FN6894.0 May 27, 2010 Driving Capacitive Loads As load capacitance increases, the -3dB bandwidth will decrease and peaking can occur" />
參數(shù)資料
型號(hào): EL5111TIWTZ-T7A
廠商: Intersil
文件頁數(shù): 4/14頁
文件大?。?/td> 0K
描述: IC OPAMP GP R-R 60MHZ SGL 5TSOT
標(biāo)準(zhǔn)包裝: 250
放大器類型: 電壓反饋
電路數(shù): 1
輸出類型: 滿擺幅
轉(zhuǎn)換速率: 100 V/µs
增益帶寬積: 32MHz
-3db帶寬: 60MHz
電流 - 輸入偏壓: 2nA
電壓 - 輸入偏移: 5000µV
電流 - 電源: 3.4mA
電流 - 輸出 / 通道: 70mA
電壓 - 電源,單路/雙路(±): 4.5 V ~ 19 V,±2.25 V ~ 9.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: SOT-23-5 細(xì)型,TSOT-23-5
供應(yīng)商設(shè)備封裝: TSOT-23-5
包裝: 帶卷 (TR)
EL5111T
12
FN6894.0
May 27, 2010
Driving Capacitive Loads
As load capacitance increases, the -3dB bandwidth will
decrease and peaking can occur. Depending on the
application, it may be necessary to reduce peaking and
to improve device stability. To improve device stability a
snubber circuit or a series resistor may be added to the
output of the EL5111T.
A snubber is a shunt load consisting of a resistor in series
with a capacitor. An optimized snubber can improve the
phase margin and the stability of the EL5111T. The
advantage of a snubber circuit is that it does not draw
any DC load current or reduce the gain.
Another method to reduce peaking is to add a series
output resistor (typically between 1Ω to 10Ω). Depending
on the capacitive loading, a small value resistor may be
the most appropriate choice to minimize any reduction in
gain.
Power Dissipation
With the high-output drive capability of the EL5111T
amplifier, it is possible to exceed the +150°C absolute
maximum junction temperature under certain load
current conditions. It is important to calculate the
maximum power dissipation of the EL5111T in the
application. Proper load conditions will ensure that the
EL5111T junction temperature stays within a safe
operating region.
The maximum power dissipation allowed in a package is
determined according to Equation 1:
where:
TJMAX = Maximum junction temperature
TAMAX = Maximum ambient temperature
ΘJA = Thermal resistance of the package
PDMAX = Maximum power dissipation allowed
The total power dissipation produced by an IC is the total
quiescent supply current times the total power supply
voltage, plus the power dissipation in the IC due to the
load, or:
when sourcing, and:
when sinking,
where:
VS = Total supply voltage (VS+ - VS-)
VS+ = Positive supply voltage
VS- = Negative supply voltage
ISMAX = Maximum supply current
(ISMAX = EL5111T quiescent current)
VOUT = Output voltage
ILOAD = Load current
Device overheating can be avoided by calculating the
minimum resistive load condition, RLOAD, resulting in
the highest power dissipation. To find RLOAD set the two
PDMAX equations equal to each other and solve for
VOUT/ILOAD. Reference the package power dissipation
curves, Figures 32 and 33, for further information.
PDMAX
TJMAX TAMAX
θJA
---------------------------------------------
=
(EQ. 1)
PDMAX
VS ISMAX V
(
S+VOUT )
ILOAD
×
+
×
=
(EQ. 2)
PDMAX
VS ISMAX V
(
OUT
VS-) ILOAD
×
+
×
=
(EQ. 3)
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0
25
50
75
100
125
150
AMBIENT TEMPERATURE (°C)
POWER
DISSIPATION
(W)
FIGURE 32. PACKAGE POWER DISSIPATION vs
AMBIENT TEMPERATURE
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
θJA = +300°C/W
TSOT5
417mW
85
FIGURE 33. PACKAGE POWER DISSIPATION vs
AMBIENT TEMPERATURE
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY (4-LAYER) TEST BOARD - EXPOSED
DIEPAD SOLDERED TO PCB PER JESD51-5
85
0.0
0.2
0.4
0.6
0.8
0
25
50
75
100
125
150
AMBIENT TEMPERATURE (°C)
POWER
DISSIPATION
(W)
θJA = +215°C/W
TSOT5
581mW
EL5111T
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