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12
FN7185.2
May 6, 2005
when sourcing, and
when sinking.
Where:
i = 1 to 2 for Dual and 1 to 4 for Quad
V
S
= Total Supply Voltage
I
SMAX
= Maximum Supply Current Per Amplifier
V
OUT
i = Maximum Output Voltage of the Application
I
LOAD
i = Load current
If we set the two P
DMAX
equations equal to each other, we
can solve for R
LOAD
i to avoid device overheat. Figure 3 and
Figure 4 provide a convenient way to see if the device will
overheat. The maximum safe power dissipation can be
found graphically, based on the package type and the
ambient temperature. By using the previous equation, it is a
simple matter to see if P
DMAX
exceeds the device's power
derating curves. To ensure proper operation, it is important
to observe the recommended derating curves shown in
Figure 3 and Figure 4.
FIGURE 3. PACKAGE POWER DISSIPATION VS AMBIENT
TEMPERATURE
FIGURE 4. PACKAGE POWER DISSIPATION VS AMBIENT
TEMPERATURE
Unused Amplifiers
It is recommended that any unused amplifiers in a dual and
a quad package be configured as a unity gain follower. The
inverting input should be directly connected to the output
and the non-inverting input tied to the ground plane.
Driving Capacitive Loads
The EL5210 and EL5410 can drive a wide range of
capacitive loads. As load capacitance increases, however,
the -3dB bandwidth of the device will decrease and the
peaking increase. The amplifiers drive 10pF loads in parallel
with 1k
with just 1.2dB of peaking, and 100pF with 6.5dB of
peaking. If less peaking is desired in these applications, a
small series resistor (usually between 5
and 50
) can be
placed in series with the output. However, this will obviously
reduce the gain slightly. Another method of reducing peaking
is to add a "snubber" circuit at the output. A snubber is a
shunt load consisting of a resistor in series with a capacitor.
Values of 150
and 10nF are typical. The advantage of a
snubber is that it does not draw any DC load current or
reduce the gain.
Power Supply Bypassing and Printed Circuit
Board Layout
The EL5210 and EL5410 can provide gain at high
frequency. As with any high-frequency device, good printed
circuit board layout is necessary for optimum performance.
Ground plane construction is highly recommended, lead
lengths should be as short as possible and the power supply
pins must be well bypassed to reduce the risk of oscillation.
For normal single supply operation, where the V
S
- pin is
connected to ground, a 0.1μF ceramic capacitor should be
placed from V
S
+ to pin to V
S
- pin. A 4.7μF tantalum
capacitor should then be connected in parallel, placed in the
region of the amplifier. One 4.7μF capacitor may be used for
multiple devices. This same capacitor combination should
be placed at each supply pin to ground if split supplies are to
be used.
P
DMAX
Σ
i V
S
I
SMAX
V
(
OUT
i
V
S
-
)
I
LOAD
i
×
–
+
×
]
=
50
150
400
800
P
Ambient Temperature (°C)
0
100
0
1200
25
75
1000
600
200
125
85
MAX T
J
=125°C
TSSOP14
θ
JA
=100°C/W
SO8
θ
JA
=110°C/W
Packages Mounted on a JEDEC JESD51-7 High Effective
Thermal Conductivity Test Board
1.0W
1.136W
909mW
833mW
SO14
θ
JA
=88°C/W
MSOP8
θ
JA
=115°C/W
50
150
400
800
P
Ambient Temperature (°C)
0
100
0
125
1200
25
75
1000
600
200
85
MAX T
J
=125°C
TSSOP14
θ
JA
=165°C/W
SO8
θ
JA
=160°C/W
MSOP8
θ
JA
=206°C/W
SO14
θ
JA
=120°C/W
Packages Mounted on a JEDEC JESD51-3 Low Effective
Thermal Conductivity Test Board
833mW
606mW
625mW
485mW
EL5210, EL5410