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參數(shù)資料
| 型號(hào)： | EL5211TIYEZ-T7 |
| 廠商： | Intersil |
| 文件頁(yè)數(shù)： | 4/15頁(yè) |
| 文件大小： | 0K |
| 描述： | IC OPAMP GP R-R 60MHZ 8MSOP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 放大器類型： | 電壓反饋 |
| 電路數(shù)： | 2 |
| 輸出類型： | 滿擺幅 |
| 轉(zhuǎn)換速率： | 100 V/µs |
| 增益帶寬積： | 32MHz |
| -3db帶寬： | 60MHz |
| 電流 - 輸入偏壓： | 2nA |
| 電壓 - 輸入偏移： | 7000µV |
| 電流 - 電源： | 6mA |
| 電流 - 輸出 / 通道： | 65mA |
| 電壓 - 電源，單路/雙路(±)： | 4.5 V ~ 19 V，±2.25 V ~ 9.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-VSSOP，8-MSOP（0.118"，3.00mm 寬）裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 8-HMSOP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | EL5211TIYEZ-T7DKR |
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EL5211T
12
FN6893.0
May 12, 2010
Driving Capacitive Loads
As load capacitance increases, the -3dB bandwidth will
decrease and peaking can occur. Depending on the
application, it may be necessary to reduce peaking and
to improve device stability. To improve device stability a
snubber circuit or a series resistor may be added to the
output of the EL5211T.
A snubber is a shunt load consisting of a resistor in series
with a capacitor. An optimized snubber can improve the
phase margin and the stability of the EL5211T. The
advantage of a snubber circuit is that it does not draw
any DC load current or reduce the gain.
Another method to reduce peaking is to add a series
output resistor (typically between 1Ω to 10Ω). Depending
on the capacitive loading, a small value resistor may be
the most appropriate choice to minimize any reduction in
gain.
Power Dissipation
With the high-output drive capability of the EL5211T
amplifiers, it is possible to exceed the +150°C absolute
maximum junction temperature under certain load
current conditions. It is important to calculate the
maximum power dissipation of the EL5211T in the
application. Proper load conditions will ensure that the
EL5211T junction temperature stays within a safe
operating region.
The maximum power dissipation allowed in a package is
determined according to Equation 1:
where:
TJMAX = Maximum junction temperature
TAMAX = Maximum ambient temperature
ΘJA = Thermal resistance of the package
PDMAX = Maximum power dissipation allowed
The total power dissipation produced by an IC is the total
quiescent supply current times the total power supply
voltage, plus the power dissipation in the IC due to the
loads, or:
when sourcing, and:
when sinking,
where:
i = 1 to 2
(1, 2 corresponds to Channel A, B respectively)
VS = Total supply voltage (VS+ - VS-)
VS+ = Positive supply voltage
VS- = Negative supply voltage
ISMAX = Maximum supply current per amplifier
(ISMAX = EL5211T quiescent current ÷ 2)
VOUT = Output voltage
ILOAD = Load current
Device overheating can be avoided by calculating the
minimum resistive load condition, RLOAD, resulting in
the highest power dissipation. To find RLOAD set the two
PDMAX equations equal to each other and solve for
VOUT/ILOAD. Reference the package power dissipation
Power Supply Bypassing and Printed Circuit
Board Layout
The EL5211T can provide gain at high frequency, so good
printed circuit board layout is necessary for optimum
performance. Ground plane construction is highly
recommended, trace lengths should be as short as
PDMAX
TJMAX TAMAX
–
θ
JA
---------------------------------------------
=
(EQ. 1)
PDMAX
ΣiV
[
S
ISMAX V
(
S+VOUTi )
ILOADi
×
–
+
×]
=
(EQ. 2)
PDMAX
ΣiV
[
S
ISMAX V
(
OUTiVS- )
ILOADi
×
–
+
×]
=
(EQ. 3)
0.0
0.2
0.4
0.6
0.8
1.0
0
25
50
75
100
125
150
AMBIENT TEMPERATURE (°C)
POWER
DISSIPATION
(W)
FIGURE 34. PACKAGE POWER DISSIPATION vs
AMBIENT TEMPERATURE
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
85
θJA = +180°C/W
HMSOP8
θJA = +160°C/W
DFN8
694mW
781mW
0.0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
0
25
50
75
100
125
150
AMBIENT TEMPERATURE (°C)
POWER
DISSIPATION
(W)
FIGURE 35. PACKAGE POWER DISSIPATION vs
AMBIENT TEMPERATURE
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY (4-LAYER) TEST BOARD - EXPOSED
DIEPAD SOLDERED TO PCB PER JESD51-5
85
θJA = +58°C/W
DFN8
θJA = +62°C/W
HMSOP8
2.16W
2.02W
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