參數(shù)資料
型號(hào): EL5225IRZ
廠商: INTERSIL CORP
元件分類: 模擬信號(hào)調(diào)理
英文描述: 10-Channel TFT-LCD Reference Voltage Generator
中文描述: SPECIALTY ANALOG CIRCUIT, PDSO24
封裝: LEAD FREE, MO-153, TSSOP-24
文件頁數(shù): 7/12頁
文件大?。?/td> 859K
代理商: EL5225IRZ
7
FN7356.0
March 11, 2004
Analog Section
TRANSFER FUNCTION
The transfer function is:
where data is the decimal value of the 10-bit data binary
input code.
The output voltages from the EL5225 will be derived from
the reference voltages present at the V
REFL
and V
REFH
pins. The impedance between those two pins is about 32k
.
Care should be taken that the system design holds these two
reference voltages within the limits of the power rails of the
EL5225. GND < V
REFH
V
S
and GND
V
REFL
V
REFH
.
In some LCD applications that require more than 10
channels, the system can be designed such that one
EL5225 will provide the Gamma correction voltages that are
more positive than the V
COM
potential. The second EL5225
can provide the Gamma correction voltage more negative
than the V
COM
potential. The Application Drawing shows a
system connected in this way.
CLOCK OSCILLATOR
The EL5225 requires an internal clock or external clock to
refresh its outputs. The outputs are refreshed at the falling OSC
clock edges. The output refreshed switches open at the rising
edges of the OSC clock. The driving load shouldn’t be changed
at the rising edges of the OSC clock. Otherwise, it will generate
a voltage error at the outputs. This clock may be input or output
via the clock pin labeled OSC. The internal clock is provided by
an internal oscillator running at approximately 21kHz and can
be output to the OSC pin. In a 2 chip system, if the driving loads
are stable, one chip may be programmed to use the internal
oscillator; then the OSC pin will output the clock from the
internal oscillator. The second chip may have the OSC pin
connected to this clock source.
For transient load application, the external clock Mode
should be used to ensure all functions are synchronized
together. The positive edge of the external clock to the OSC
pin should be timed to avoid the transient load effect. The
Application Drawing shows the LCD H rate signal used, here
the positive clock edge is timed to avoid the transient load of
the column driver circuits.
After power on, the chip will start with the internal oscillator
mode. At this time, the OSC pin will be in a high impedance
condition to prevent contention. By setting B14 to high, the
chip is on external clock mode. Setting B14 to low, the chip is
on internal clock mode.
TABLE 2. SERIAL TIMING PARAMETERS
PARAMETER
RECOMMENDED OPERATING RANGE
DESCRIPTION
T
200ns
Clock Period
t
r
/t
f
0.05 * T
Clock Rise/Fall Time
t
HE
10ns
ENA Hold Time
t
SE
10ns
ENA Setup Time
t
HD
10ns
Data Hold Time
t
SD
10ns
Data Setup Time
t
W
0.50 * T
Clock Pulse Width
TABLE 3. SERIAL PROGRAMMING EXAMPLES
CONTROL
CHANNEL ADDRESS
DATA
CONDITION
C1
C0
A3
A2
A1
A0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Internal Oscillator, Channel A, Value = 0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
Internal Oscillator, Channel A, Value = 1023
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
Internal Oscillator, Channel A, Value = 512
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
1‘t
Internal Oscillator, Channel C, Value = 513
0
0
0
1
1
1
0
0
0
0
0
1
1
1
1
1
Internal Oscillator, Channel H, Value = 31
0
1
0
1
1
1
0
0
0
0
0
1
1
1
1
1
External Oscillator, Channel H, Value = 31
V
OUT IDEAL
)
V
REFL
=
------------
V
REFH
- V
REFL
(
)
×
+
EL5225
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