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參數(shù)資料
| 型號(hào)： | EL5281CS |
| 廠商： | ELANTEC |
| 元件分類(lèi)： | 比較器 |
| 英文描述： | Replaced by PTN04050A : |
| 中文描述： | DUAL COMPARATOR, 4000 uV OFFSET-MAX, 8 ns RESPONSE TIME, PDSO14 |
| 封裝： | SO-14 |
| 文件頁(yè)數(shù)： | 6/9頁(yè) |
| 文件大?。?/td> | 161K |
| 代理商： | EL5281CS |
6
Timing Diagram
V
IN
V
OD
t
H
t
S
t
PD
-
t
PW
(D)
t
d
+
Latch
Enable
Input
Latch
Compare
Latch
Latch
Compare
Differenti
al Input
Voltage
Comparator
Output
1.4V
V
OS
2.4V
Definition of Terms
TERMS
DEFINITION
V
OS
Input Offset Voltage - Voltage applied between the two input terminals to obtain CMOS logic threshold at the output
V
IN
Input Voltage Pulse Amplitude - Usually set to 1V for comparator specifications
V
OD
Input Voltage Overdrive - Usually set to 50mV and in opposite polarity to VIN for comparator specifications
t
PD
+
Input to Output High Delay - The propagation delay measured from the time the input signal crosses the input offset voltage to
the CMOS logic threshold of an output low to high transition
t
PD
-
Input to Output Low Delay - The propagation delay measured from the time the input signal crosses the input offset voltage to
the CMOS logic threshold of an output high to low transition
t
D
+
Latch Disable to Output High Delay - The propagation delay measured from the latch signal crossing the CMOS threshold in
a low to high transition to the point of the output crossing CMOS threshold in a low to high transition
t
D
-
Latch Disable to Output Low Delay - The propagation delay measured from the latch signal crossing the CMOS threshold in a
low to high transition to the point of the output crossing CMOS threshold in a high to low transition
t
S
Minimum Setup Time - The minimum time before the negative transition of the latch signal that an input signal change must be
present in order to be acquired and held at the outputs
t
H
Minimum Hold Time - The minimum time after the negative transition of the latch signal that an input signal must remain
unchanged in order to be acquired and held at the output
t
PW
(D)
Minimum Latch Disable Pulse Width - The minimum time that the latch signal must remain high in order to acquire and hold an
input signal change
EL5281
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EL5281CS-T13 | Replaced by PTN04050A : |
| EL5281CS-T7 | Replaced by PTN04050A : |
| EL5283CY-T13 | Window 8ns High-Speed Comparator |
| EL5283 | Replaced by PTN04050A : |
| EL5283CY | Replaced by PTN04050A : |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EL5281CS-T13 | 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:Dual 8ns High-Speed Comparator |
| EL5281CS-T7 | 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:Dual 8ns High-Speed Comparator |
| EL5283 | 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:Window 8ns High-Speed Comparator |
| EL5283C | 制造商:ELANTEC 制造商全稱(chēng):ELANTEC 功能描述:Dual and Window 8ns High-Speed Comparators |
| EL5283CY | 制造商:ELANTEC 制造商全稱(chēng):ELANTEC 功能描述:Dual and Window 8ns High-Speed Comparators |
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