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參數(shù)資料
| 型號(hào)： | EL5625 |
| 廠商： | Intersil Corporation |
| 英文描述： | Programmable 18-Channel Gamma with 1-Channel VCOM with Reference |
| 中文描述： | 可編程18通道伽馬1通道威科姆與參考 |
| 文件頁(yè)數(shù)： | 9/11頁(yè) |
| 文件大小： | 478K |
| 代理商： | EL5625 |
9
FN7488.0
February 28, 2006
CHANNEL OUTPUTS
Each of the channel outputs has a rail-to-rail buffer. This
enables all channels to have the capability to drive to within
50mV of the power rails, (see Electrical Characteristics for
details).
When driving large capacitive loads, a series resistor should
be placed in series with the output (Usually between 5
and
50
).
Each of the channels is updated on a continuous cycle, the
time for the new data to appear at a specific output will
depend on the exact timing relationship of the incoming data
to this cycle.
The best-case scenario is when the data has just been
captured and then passed on to the output stage
immediately; this can be as short as 48μs. In the worst-case
scenario, this will be 860μs for EL5625, when the data has
just missed the cycle at f_OSC = 21kHz.
When a large change in output voltage is required, the
change will occur in 2V steps, thus the requisite number of
timing cycles will be added to the overall update time. This
means that a large change of 16V can take between 6.8ms
and 7.2ms depending on the absolute timing relative to the
update cycle.
Output Stage and the Use of External
Oscillator
Simplified output sample and hold amp stage for one
channel.
The output voltage is generated from the DAC, which is V
IN
in the above circuit. The refreshed switches are controlled by
the internal or external oscillator signal. When the OSC clock
signal is low, switches S
1
and S
2
are closed. The output
V
OUT
= V
IN
and at the same time the sample and hold cap
CH is being charged. When the OSC clock signal is high, the
refreshed switches S
1
and S
2
are opened and the output
voltage is maintained by CH. This refreshed process will
repeat every 18 clock cycles for each channel. The time
takes to update the output depends on the timing at the V
IN
and the state of the switches. It can take 1 to 19 clock cycles
to update each output.
For the sample and hold capacitor CH to maintain the
correct output voltage, the driving load shouldn’t be changed
at the rising edge of the OSC signal. Since at the rising edge
of the OSC clock, the refreshed switches are being opened,
if the load changes at that time, it will generate an error
output voltage. For a fixed load condition, the internal
oscillator can be used.
For the transient load condition, the external OSC mode
should be used to avoid the conflict between the rising edge
of the OSC signal and the changing load. So a timing delay
circuit will be needed to delay the OSC signal and avoid the
rising edge of the OSC signal and changing the load at the
same time.
TRANSIENT LOAD RESPONSE
Channel 3 --- sinking and sourcing 5mA current
Channel 2 --- EXT_OSC signal
Channel 1 --- V
OUT
Here, the OSC signal is synchronized to the load signal. The
rising edge of the OSC signal is then delayed by some
amount of time and gives enough time for CH to be charged
to a new voltage before the switches are opened.
CHANNEL TO CHANNEL REFRESH
Ch1 --- Output1
Ch3 --- Output2
Ch2 --- EXT_OSC
-
+
V
OUT
1.3V
FIGURE 8.
S
1
-
+
V
IN
S
2
-
+
CH
OSC
1.3V
FIGURE 9.
FIGURE 10.
EL5625
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