參數(shù)資料
型號： EL5825IRZ-T7
廠商： INTERSIL CORP
元件分類： 模擬信號調(diào)理
英文描述： 8-Channel TFT-LCD Reference Voltage Generator
中文描述： SPECIALTY ANALOG CIRCUIT, PDSO24
封裝： ROHS COMPLIANT, MO-153, TSSOP-24
文件頁數(shù)： 2/12頁
文件大小： 638K
代理商： EL5825IRZ-T7
2
FN7005.4
June 24, 2005
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: T
J
= T
C
= T
A
Absolute Maximum Ratings
(T
A
= 25°C)
Supply Voltage between V
S
and GND. . . . . . . . . . . . . . . . . . . .+18V
Supply Voltage between V
SD
and GND . . . . . . . V
S
and +7V (max)
Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 30mA
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . .125°C
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
V
S
= 15V, V
SD
= 5V, V
REFH
= 13V, V
REFL
= 2V,
R
L
= 1.5k
and
C
L
= 200pF to 0V, T
A
= 25°C, unless
otherwise specified.
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
I
S
Supply Current
No load
7.6
9
mA
I
SD
Digital Supply Current
0.17
0.35
mA
ANALOG
V
OL
Output Swing Low
Sinking 5mA (V
REFH
= 15V, V
REFL
= 0)
50
150
mV
V
OH
Output Swing High
Sourcing 5mA (V
REFH
= 15V, V
REFL
= 0)
14.85
14.95
V
I
SC
Short Circuit Current
R
L
= 10
100
140
mA
PSRR
Power Supply Rejection Ratio
V
S
+ is moved from 14V to 16V
45
60
dB
t
D
Program to Out Delay
4
ms
V
AC
Accuracy
20
mV
V
DROOP
Droop Voltage
1
2
mV/ms
R
INH
Input Resistance @ V
REFH
, V
REFL
34
k
REG
Load Regulation
I
OUT
= 5mA step
0.5
1.5
mV/mA
BG
Band Gap
1.1
1.3
1.6
V
DIGITAL
V
IH
Logic 1 Input Voltage
V
SD
-
20%
V
V
IL
Logic 0 Input Voltage
20%*
V
SD
V
F
CLK
Clock Frequency
5
MHz
t
S
Setup Time
20
ns
t
H
Hold Time
20
ns
t
LC
Load to Clock Time
20
ns
t
CE
Clock to Load Line
20
ns
t
DCO
Clock to Out Delay Time
Negative edge of SCLK
10
ns
R
SDIN
S
DIN
Input Resistance
1
G
EL5825
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