12 Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certificat" />
參數(shù)資料
型號(hào): EL8170FSZ
廠商: Intersil
文件頁數(shù): 4/13頁
文件大?。?/td> 0K
描述: IC AMP INSTR SGL R-R I/O 8-SOIC
標(biāo)準(zhǔn)包裝: 97
放大器類型: 儀表
電路數(shù): 1
輸出類型: 滿擺幅
轉(zhuǎn)換速率: 0.55 V/µs
-3db帶寬: 192kHz
電流 - 輸入偏壓: 700pA
電壓 - 輸入偏移: 50µV
電流 - 電源: 65µA
電流 - 輸出 / 通道: 32mA
電壓 - 電源,單路/雙路(±): 2.4 V ~ 5.5 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SOIC
包裝: 管件
產(chǎn)品目錄頁面: 1234 (CN2011-ZH PDF)
EL8170, EL8173
12
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7490.7
October 15, 2013
For additional products, see www.intersil.com/en/products.html
.
External Resistor Mismatches
Because of the independent pair of feedback terminals provided
by the EL8170 and EL8173, the CMRR is not degraded by any
resistor mismatches. Hence, unlike a three op amp and
especially a two op amp in-amp, the EL8170 and EL8173 reduce
the cost of external components by allowing the use of 1% or
more tolerance resistors without sacrificing CMRR performance.
The EL8170 and EL8173 CMRR is maintained regardless of the
tolerance of the resistors used.
Gain Error and Accuracy
The EL8173 has a Gain Error, EG, of 0.2% typical. The EL8170 has
an EG of 0.3% typical. The gain error indicated in the “Electrical
Specifications” table on page 2 is the inherent gain error of the
EL8170 and EL8173 and does not include the gain error
contributed by the resistors. There is an additional gain error due
to the tolerance of the resistors used. The resulting non-ideal
transfer function effectively becomes Equation 4:
Where:
ERG = Tolerance of RG
ERF = Tolerance of RF
EG = Gain Error of the EL8170 or EL8173
The term [1 - (ERG + ERF + EG)] is the deviation from the
theoretical gain. Thus, (ERG + ERF + EG) is the total gain error. For
example, if 1% resistors are used for the EL8170, the total gain
error would be as shown in Equation 5:
Power Dissipation
It is possible to exceed the +150°C maximum junction
temperatures under certain load and power-supply conditions. It
is therefore important to calculate the maximum junction
temperature (TJMAX) for all applications to determine if power
supply voltages, load conditions, or package type need to be
modified to remain in the safe operating area. These parameters
are related in Equation 6:
where:
PDMAXTOTAL is the sum of the maximum power dissipation of
each amplifier in the package (PDMAX)
PDMAX for each amplifier can be calculated as shown in
Equation 7:
where:
TMAX = Maximum ambient temperature
θJA = Thermal resistance of the package
PDMAX = Maximum power dissipation of 1 amplifier
VS = Supply voltage (Magnitude of V+ and V-)
IMAX = Maximum supply current of 1 amplifier
VOUTMAX = Maximum output voltage swing of the application
RL = Load resistance
FIGURE 39. REFERENCE CONNECTION WITH AN AVAILABLE VREF
1
3
2
8
5
4
7
6
+
-
+
-
IN+
IN-
FB+
FB-
V+
V-
RF
RG
VOUT
EL8170,
VCM
VIN/2
VREF
+2.4V TO +5.5V
EL8173
V
OUT
1
R
F
R
G
--------
+
V
IN
()
V
REF
()
+
=
(EQ. 3)
V
OUT
1
R
F
R
G
--------
+
1E
RG
E
RF
E
G
++
()
[] V
IN
×
=
(EQ. 4)
E
RG
E
RF
E
G typical
()
++
()
±
=
0.01
0.003
++
()
±
=
2.3%
±
=
(EQ. 5)
T
JMAX
T
MAX
θ
JAxPDMAXTOTAL
()
+
=
(EQ. 6)
PD
MAX
2*V
S
I
SMAX
V
S
(
- V
OUTMAX )
V
OUTMAX
R
L
----------------------------
×
+
×
=
(EQ. 7)
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