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參數(shù)資料
| 型號： | EL8300ISZ-T7 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 2/14頁 |
| 文件大小： | 0K |
| 描述： | IC AMP TRIPLE 200MHZ R-R 16-SOIC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 放大器類型： | 電壓反饋 |
| 電路數(shù)： | 3 |
| 輸出類型： | 滿擺幅 |
| 轉(zhuǎn)換速率： | 200 V/µs |
| 增益帶寬積： | 100MHz |
| -3db帶寬： | 200MHz |
| 電流 - 輸入偏壓： | 1.4µA |
| 電壓 - 輸入偏移： | 800µV |
| 電流 - 電源： | 2mA |
| 電流 - 輸出 / 通道： | 65mA |
| 電壓 - 電源，單路/雙路(±)： | 3 V ~ 5 V，±1.5 V ~ 2.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | EL8300ISZ-T7DKR |
10
Driving Capacitive Loads and Cables
The EL8100, EL8101 can drive 10pF loads in parallel with
1k
with less than 5dB of peaking at gain of +1. If less
peaking is desired in applications, a small series resistor
(usually between 5
to 50) can be placed in series with the
output to eliminate most peaking. However, this will reduce
the gain slightly. If the gain setting is greater than 1, the gain
resistor RG can then be chosen to make up for any gain loss
which may be created by the additional series resistor at the
output.
When used as a cable driver, double termination is always
recommended for reflection-free performance. For those
applications, a back-termination series resistor at the
amplifier’s output will isolate the amplifier from the cable and
allow extensive capacitive drive. However, other applications
may have high capacitive loads without a back-termination
resistor. Again, a small series resistor at the output can help
to reduce peaking.
Disable/Power-Down
The EL8300 can be disabled and placed its output in a high
impedance state. The turn off time for each channel is about
25ns and the turn on time is about 200ns. When disabled,
the amplifier’s supply current is reduced to 30A typically,
thereby effectively eliminating the power consumption. The
amplifier’s power down can be controlled by standard TTL or
CMOS signal levels at the ENABLE pin. The applied logic
signal is relative to VS- pin. Letting the ENABLE pin float or
applying a signal that is less than 0.8V above VS- will enable
the amplifier. The amplifier will be disabled when the signal
at ENABLE pin is 2V above VS-.
Output Drive Capability
The EL8300 does not have internal short circuit protection
circuitry. They have a typical short circuit current of 70mA
sourcing and 140mA sinking for the output is connected to
half way between the rails with a 10
resistor. If the output is
shorted indefinitely, the power dissipation could easily
increase such that the part will be destroyed. Maximum
reliability is maintained if the output current never exceeds
±40mA. This limit is set by the design of the internal metal
interconnections.
Power Dissipation
With the high output drive capability of the EL8300, it is
possible to exceed the 125
°C absolute maximum junction
temperature under certain load current conditions.
Therefore, it is important to calculate the maximum junction
temperature for the application to determine if the load
conditions or package types need to be modified for the
amplifier to remain in the safe operating area.
The maximum power dissipation allowed in a package is
determined according to:
Where:
TJMAX = Maximum junction temperature
TAMAX = Maximum ambient temperature
θJA = Thermal resistance of the package
The maximum power dissipation actually produced by an IC
is the total quiescent supply current times the total power
supply voltage, plus the power in the IC due to the load, or:
For sourcing:
For sinking:
Where:
VS = Total supply voltage
ISMAX = Maximum quiescent supply current
VOUTi = Maximum output voltage of the application for
each channel
RLOADi = Load resistance tied to ground for each channel
ILOADi = Load current for each channel
By setting the two PDMAX equations equal to each other, we
can solve the output current and RLOADi to avoid the device
overheat.
Power Supply Bypassing and Printed Circuit
Board Layout
As with any high frequency device, a good printed circuit
board layout is necessary for optimum performance. Lead
lengths should be as sort as possible. The power supply pin
must be well bypassed to reduce the risk of oscillation. For
normal single supply operation, where the VS- pin is
connected to the ground plane, a single 4.7F tantalum
capacitor in parallel with a 0.1F ceramic capacitor from VS+
to GND will suffice. This same capacitor combination should
be placed at each supply pin to ground if split supplies are to
be used. In this case, the VS- pin becomes the negative
supply rail.
For good AC performance, parasitic capacitance should be
kept to a minimum. Use of wire wound resistors should be
avoided because of their additional series inductance. Use
of sockets should also be avoided if possible. Sockets add
parasitic inductance and capacitance that can result in
compromised performance. Minimizing parasitic capacitance
at the amplifier’s inverting input pin is very important. The
feedback resistor should be placed very close to the
inverting input pin. Strip line design techniques are
recommended for the signal traces.
PD
MAX
T
JMAX
T
AMAX
–
θ
JA
---------------------------------------------
=
PD
MAX
V
S
I
SMAX
V
S
V
OUTi
–
()
V
OUTi
R
Li
-----------------
×
i1
=
3
∑
+
×
=
PD
MAX
V
S
I
SMAX
V
OUTi
V
S-
–
() I
LOADi
×
i1
=
3
∑
+
×
=
EL8300
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