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參數(shù)資料
| 型號(hào)： | EL9115IL-T13 |
| 廠商： | INTERSIL CORP |
| 元件分類(lèi)： | 消費(fèi)家電 |
| 英文描述： | Triple Analog Video Delay Line |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, QCC20 |
| 封裝： | 5 X 5 MM, QFN-20 |
| 文件頁(yè)數(shù)： | 2/9頁(yè) |
| 文件大?。?/td> | 581K |
| 代理商： | EL9115IL-T13 |
2
FN7441.2
September 8, 2005
Absolute Maximum Ratings
(T
A
= 25°C)
Supply Voltage (V
S
+ to V
S
-) . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V
Maximum Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . ±60mA
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . .+135°C
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: T
J
= T
C
= T
A
DC Electrical Specifications
V
SA
+
= V
A
+
= +5V, V
SA
-
= V
A
-
= -5V, T
A
= 25°C, exposed die plate = -5V, unless otherwise specified.
PARAMETER
DESCRIPTION
CONDITION
MIN
TYP
MAX
UNIT
V+
Positive Supply Range
+4.5
+5.5
V
V-
Negative Supply Range
-4.5
-5.5
V
G_0
Gain Zero Delay
X2 = 5V, 150
load
1.81
1.89
2.04
G_m
Gain Mid Delay
1.66
1.84
2.04
G_f
Gain Full Delay
1.52
1.79
2.04
DG_m0
Difference in Gain, 0 - Mid
-7.5
-2.5
2.5
%
DG_f0
Difference in Gain, 0 - Full
-13.5
-6.0
2.5
%
DG_fm
Difference in Gain, Mid - Full
-10.0
-2.6
4.0
%
V
IN
Input Voltage Range
Gain falls to 90% of nominal
-0.7
1.3
V
V
OUT
Output Voltage Range
X2 = +5V into 150
load
-5
1.6
V
I
B
Input Bias Current
1
5
μA
R
IN
Input Resistance
10
M
V
OS_0
Output Offset 0 Delay
X2 = +5V, 75 + 75
load
-200
-150
60
mV
V
OS_M
Output Offset full Delay
-200
-140
60
mV
V
OS_F
Output Offset mid Delay
-200
-130
60
mV
Z
OUT
Output Impedance
Chip enable = +5V
4.5
4.8
5.1
Chip enable = 0V
1
M
+PSRR
Rejection of Positive Supply
X2 = +5V into 75 + 75
load
-38
dB
-PSRR
Rejection of Negative Supply
X2 = +5V into 75 + 75
load
-53
dB
I
SP
Supply Current (Note 1)
Chip enable = +5V current on V
SP
75
87
115
mA
I
SM
Supply Current (Note 1)
Chip enable = +5V current in V
SM
-10.5
-8.6
-7
mA
I
SMO
Supply Current (Note 1)
Chip enable = +5V current in V
SMO
-13
-11.6
-10
mA
I
SPO
Supply Current (Note 1)
Chip enable = +5V current in V
SPO
10
11.8
15.5
I
SP
Supply Current (Note 1)
Increase in I
SP
per unit step in delay
0.9
mA
I
SP OFF
Supply Current (Note 1)
Chip enable = 0V current in V
SP
1.6
mA
I
OUT
Output Drive Current
10
load, 0.5V drive, X2 = 5V
30
mA
L
HI
Logic High
Switch high threshold
1.25
1.6
V
L
LO
Logic Low
Switch low threshold
0.8
1.15
V
NOTE:
1. All supply currents measured withe Delay R = 0ns, G = mid delay, B = full delay.
EL9115
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