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參數(shù)資料
| 型號(hào)： | EL9115ILZ-T7 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 9/10頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ANALOG DELAY LINE TRPL 20-QFN |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 視頻延遲線 |
| 應(yīng)用： | 模擬波速合成，失真控制 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-VQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 20-QFN（5x5） |
| 包裝： | 帶卷 (TR) |
8
FN7441.7
January 12, 2012
shifted directly to the final registers as it is clocked in. Initial
value of all registers on power-up is 0. It is the user's
responsibility to send complete patterns of 8 clock cycles,
even if the first bit is set to 1. If less than 8 bits are sent, data
will only be partially shifted through the registers. The pattern
of 8 starts with NSEnable going low, so it is good practice to
frame each word within an NS enable burst.
Test Pins
Three test pins are provided (Test R, Test G, Test B). During
normal operation, the test pins output pulses of current for a
duration of the overlap between the inputs, as shown in
Figure 15:
Test_R pulse = Red out (A) wrt Green out (B)
Test_G pulse = Green out
wrt Blue out
Test_B pulse = Blue out
wrt Red out
Averaging the current gives a direct measure of the delay
between the two edges. When A precedes B the current
pulse is +50A, and the output voltage goes up. When B
precedes A, the pulse is -50A.
For the logic to work correctly, A and B must have a period of
overlap while they are high (a delay longer than the pulse
width cannot be measured).
Signals A and B are derived from the video input by
comparing the video signal with a slicing level, which is set by
an internal DAC. This enables the delay to be measured
either from the rising edges of sync-like signals encoded on
top of the video or from a dedicated set-up signal. The outputs
can be used to set the correct delays for the signals received.
The DAC level is set through the serial input by bits 1
through 4 directed to the test register (00). Table 2 shows the
settings for the DAC slice level bits.
Test Mode
Bit zero of the test register is set to 0 for normal operation. If
it is set to 1 then the device is in Test Mode. In Test Mode,
the DAC voltage is directed to the Green channel output,
while for the Red and Blue channels, the test outputs are
now pulses of current which are generated by looking at the
delay between the input and output of the channel. They
thus enable the delay to be measured.
NSENABLE
SCLOCK
SDATA
A1
A0
D4
D3
D2
D1
D0
0
a
b
v
w
x
y
z
FIGURE 14. SERIAL DATA TIMING
EL9115
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