參數資料
型號： ELANSC300-25KI
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： Highly Integrated, Low-Power, 32-Bit Microcontroller
中文描述： 32-BIT, 25 MHz, MICROCONTROLLER, PQFP208
封裝： SHRINK, PLASTIC, QFP-208
文件頁數： 49/139頁
文件大小： 1388K
代理商： ELANSC300-25KI
élanSC300 Microcontroller Data Sheet
49
P R E L I M I N A R Y
See Table 11 for a description of the physical organization of the DRAM devices supported.
Bit 0 of the Memory Configuration 1 Register, Index 66h must be set to enable Enhanced Page mode. Bit 1 of the Memory Con-
figuration 1 Register, Index 66h, must be set for DRAM. If set for SRAM, bits 0 and 1 control wait states.
SRAM
When using SRAM instead of DRAM for main memory,
up to 16 Mbyte can be accessed, the SRAM being or-
ganized as one or two banks. Each bank is 16 bits wide
and is provided with a low and high byte select.
Notes:
1. Bit 4 of the Version Register, Index 64h must also be set for 2-Mbyte Enhanced Page mode. Also, bit 0 of Memory Configu-
ration 1 Register, Index 66h, must be a 1.
2. When 16-Mbit asymmetric DRAMs are used in a two-bank configuration (4 Mbyte), bits 1 and 0 of the Memory Configuration 1
Register, Index 66h, must be set for Enhanced Page mode only.
An SRAM memory interface is selected by setting bit 0
of the Miscellaneous 6 Register, Index 70h. If this is
done, CAS1H, CAS1L, CAS0H, and CAS0L will have
their alternate function as SRAM chip select pins 3–0
(SRCS3–SRCS0). Table 18 shows the key SRAM ac-
cess pins.
See Table 15 on page 47 for bank size settings.
The MS2–MS0 bits in the Memory Configuration Reg-
ister, Index 66, are also used to program the total
SRAM size. Bit 7 of the PCMCIA Card Reset Register,
Index B4h, must be cleared for SRAM configurations.
Table 19 contains information about SRAM wait state
logic, and Table 30 on page 71 contains SRAM inter-
face alternate pin information.
Table 17.
DRAM Address Translation (Enhanced Page Mode)
Index
B4h
Bit
7
0
Index
66h
Bits
4 3 2
0 1 0
1
Index
B1h
Bits
7 6
x x
DRAM
DRAM Address
Size
(Byte)
2M
Bank 0
(Byte)
1M
Bank 1
(Byte)
1M
RAS
CAS
RAS
CAS
RAS
CAS
RAS
CAS
RAS
CAS
RAS
CAS
MA11MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0
–
–
–
–
–
–
–
–
A20
–
–
–
–
–
A22
A11
–
–
A21
–
A19
–
A19
A10
A19
A10
–
–
A19
–
A18
A9
A18
A9
A18
A9
A18
A9
A18
–
A17
A8
A17
A8
A17
A8
A17
A8
A17
A8
A16
A7
A16
A7
A16
A7
A16
A7
A16
A7
A15
A6
A15
A6
A15
A6
A15
A6
A15
A6
A14
A5
A14
A5
A14
A5
A14
A5
A14
A5
A13
A4
A13
A4
A13
A4
A13
A4
A13
A4
A12
A3
A12
A3
A23
A3
A12
A3
A12
A3
A11
A2
A21
A2
A21
A2
A11
A2
A11
A2
A20
A1
A20
A1
A20
A1
A19
A1
A10
A1
0
1 0 0
x x
4M
2M
2M
0
1 1 0
x x
16M
8M
8M
1
x x x
0 1
1M
512K
512K
1
x x x
2
1 1
4M
2M
2M
Table 18.
SRAM Access Pins
Pin Name
SRCS0
SRCS1
SRCS2
SRCS3
SA23–SA1
MWE
I/O
O
O
O
O
O
O
Function
SRAM Bank 0 Low Byte Select
SRAM Bank 0 High Byte Select
SRAM Bank 1 Low Byte Select
SRAM Bank 1 High Byte Select
Address (16 Mbyte maximum)
Write enable
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