參數(shù)資料
型號： ELANSC300-25VI
廠商： Advanced Micro Devices, Inc.
元件分類： 32位微控制器
英文描述： Highly Integrated, Low-Power, 32-Bit Microcontroller
中文描述： 高度集成，低功耗，32位微控制器
文件頁數(shù)： 54/139頁
文件大小： 1388K
代理商： ELANSC300-25VI
54
élanSC300 Microcontroller Data Sheet
P R E L I M I N A R Y
Notes:
All power management features will be disabled when AC power is detected via the ACIN pin being High. A register is provided
to implement “software ACIN” by writing 1 to bit 5 in the Miscellaneous 6 Register, Index 70h.
The DMA clock can be stopped except during DMA transfers. The Function Enable Register, Index B0h, controls this function.
The CPU clock speed in Low-Speed PLL mode is selectable, (see the PMU Control 3 Register, Index ADh).
The CPU Clock speed:
1. Can be programmed to run intermittently (on IRQ0) at 9.2 MHz.
2. Programmable option (but not on per-clock basis; i.e., all clocks with this note are controlled by a single ON/OFF select for
that PMU mode).
3. Programmable option, will reflect setting in Suspend mode.
4. Can be programmed to run at 9.2 MHz during temporary-on NMI/SMI handlers.
Table 22.
PMU Modes
Mode
Description
Power On
High-Speed PLL
After Power-on reset, system enters High-Speed PLL mode.
The system will be in this mode as long as activities are detected by activity monitor (described in the Pro-
grammable Activity Mask Registers, Indexes 08h, 75h, and 76h).
The system will enter this mode from High-Speed PLL mode after a programmable 1/512 s to 1/2 s, or
1/16 s to 16 s of inactivity.
The system will enter this mode from Low-Speed PLL mode after a programmable 1/16 s to 16 s, or
1/2 s to 128 s of inactivity.
The system will enter this mode from Doze mode after a programmable 4 s to 17 minutes of inactivity.
The system will enter this mode from Sleep mode after a programmable 1/16 s to 16 s of inactivity.
The system will enter this mode from Suspend mode after a programmable 1 to 256 minutes of inactivity.
Low-Speed PLL
Doze
Sleep
Suspend
Off
Table 23.
Internal Clock States
Mode
High-Speed
CPU CLK
33/25/20 MHz
Low-Speed
CPU CLK
9.2 MHz
VIDEO CLK
DMA CLK
SYSCLK
8254 CLK
(Timer)
1.19 MHz
16450 CLK
(UART)
1.8432 MHz
High-Speed
PLL
Low-Speed
PLL
14.336 MHz
4.6 MHz
9.2 MHz
4.608/2.304/
1.152/0.567 MHz
4.608/2.304/
1.152/0.567 MHz
14.336 MHz
2.3/1.2/
0.58/0.29
MHz
9.2 MHz
1.19 MHz
1.8432 MHz
Doze
DC
1
DC
DC
1
14.3 MHz/DC
2
DC
1
9.2 MHz/DC
2
1.19 MHz/DC
2
1.8 MHz/DC
2
DC
1.19 MHz/DC
2
1.8 MHz/DC
2
DC
1.19 MHz/DC
2
1.8 MHz/DC
2
DC
1.19 MHz/DC
3
1.8 MHz/DC
3
Sleep
9.2 MHz/DC
4
14.3 MHz/DC
2
4.6 MHz/DC
4
Suspend
DC
9.2 MHz/DC
4
14.3 MHz/DC
2
4.6 MHz/DC
4
Off
DC
9.2 MHz/DC
4
14.3 MHz/DC
3
4.6 MHz/DC
4
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