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| 型號(hào)： | ELANSC300-33KI |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Highly Integrated, Low-Power, 32-Bit Microcontroller |
| 中文描述： | 32-BIT, 33 MHz, MICROCONTROLLER, PQFP208 |
| 封裝： | SHRINK, PLASTIC, QFP-208 |
| 文件頁(yè)數(shù)： | 110/139頁(yè) |
| 文件大小： | 1388K |
| 代理商： | ELANSC300-33KI |
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110
élanSC300 Microcontroller Data Sheet
P R E L I M I N A R Y
Notes:
1. These timings are always controlled via refresh cycle generation and are therefore based on the programmed refresh rate for
the system. LVEE active always follows LVDD active by one refresh cycle. This sequence will always occur when the system
exits reset or when the system transitions from the Suspend mode to High-Speed PLL mode. The default refresh rate after
reset is 15.0
μ
s. See the
élan
TM
SC300 Microcontroller Programmer’s Reference Manual
, order #18470,
for a full description
of the power management unit and the refresh control mechanisms.
2. LVEE will always be forced to inactive whenever the device enters the Sleep mode, or whenever the Video PLL is forced off
in Doze mode. LVEE will remain inactive in Suspend mode. LVDD will remain active until the device enters the Suspend
mode, at which point it will be forced inactive.
3. The LCD panel data and control signals are all forced to a logical 0 in the power management modes that are programmed
to disable the video PLL (i.e., the video PLL may be disabled in Doze, Sleep, and Suspend modes). These signals will be re-
driven whenever LVDD is driven active.
Table 58.
Video RAM/LCD Interface (See Figures 41 and 42)
Symbol
Parameter Description
Notes
Preliminary
Unit
Min
Max
t81
t82
t83
t84
t85
t86
t87
t88
t89
t90
t91
t92
t93
t94
t95
t96
t97
DSMD hold from DSMA change
Display RAM read cycle pulse width
DSMD active from DSWE active
DSMD setup to DSWE inactive
DSMA hold from DSWE inactive
DSMD hold from DSWE inactive
Display RAM write cycle pulse width
DSMD tri-state delay from DSOE High
DSMD delay from DSOE active
Panel data setup to CP2 (data clock)
Panel data hold from CP2 (data clock)
Panel data delay from CP2 (data clock)
CP2 allowance time from CP1 (latch pulse)
CP1 allowance time from CP2
FRM setup time
FRM hold time
DSMA setup to DSWE active
5
85
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
50
15
5
0
65
5
5
5
10
30
30
10
65
65
520
520
0
Table 59.
Power Management Control Signals (Not Shown)
No.
Parameter Description
Notes
Preliminary
Units
Min
Max
EXTSMI pulse width
SUS/RES pulse width
LVDD active Low to LVEE active Low
LVEE inactive to LVDD inactive
10
100
ns
ns
1, 3
2, 3
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ELANSC300-33VC | Highly Integrated, Low-Power, 32-Bit Microcontroller |
| ELANSC300 | Highly Integrated, Low-Power, 32-Bit Microcontroller |
| ELANSC300-25KC | Highly Integrated, Low-Power, 32-Bit Microcontroller |
| ELANSC300-25KI | Highly Integrated, Low-Power, 32-Bit Microcontroller |
| ELANSC300-25VC | Highly Integrated, Low-Power, 32-Bit Microcontroller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ELANSC300-33VC | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Advanced Micro Devices 功能描述: 制造商:AMD 功能描述: |
| ELANSC300-33VI | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Highly Integrated, Low-Power, 32-Bit Microcontroller |
| ELANSC300WW WAF | 制造商:Advanced Micro Devices 功能描述: |
| ELANSC310 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Elan SC310 - Elan SC310 Single-Chip. 32-Bit. PC/AT Microcontroller |
| ELANSC310-25 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Single-Chip, 32-Bit, PC/AT Microcontroller |
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