參數(shù)資料
型號: ELANSC300-33VC
廠商: ADVANCED MICRO DEVICES INC
元件分類: 微控制器/微處理器
英文描述: Highly Integrated, Low-Power, 32-Bit Microcontroller
中文描述: 32-BIT, 33 MHz, MICROCONTROLLER, PQFP208
封裝: TQFP-208
文件頁數(shù): 70/139頁
文件大?。?/td> 1388K
代理商: ELANSC300-33VC
70
élanSC300 Microcontroller Data Sheet
P R E L I M I N A R Y
Maximum ISA Interface versus Internal LCD Interface
The maximum ISA interface alternate functions are configured via the DTR and RTS
pin states when the élanSC300
microcontroller is reset.
Notes:
See the External Resistor Requirements section for information on required termination for Maximum ISA Bus and Internal LCD
Controller modes.
Table 29.
Pins Shared Between Maximum ISA Bus and Internal LCD Interface Functions
ISA Interface Pin Name
Pin Type
ISA Interface Pin Description/Notes
Internal LCD Controller
Mode Function Pin Name
LCDD2
LVDD
DSMD6
Pin No.
IOCHCHK
BALE
DRQ0
I
ISA I/O Channel Check input
ISA Bus Address Latch Enable
DMA Channel 0 Request
177
O
145
I
171
DRQ1
DRQ3
DRQ5
DRQ6
DRQ7
DACK0
DACK1
DACK3
DACK5
DACK6
DACK7
IRQ4
IRQ5
IRQ7
IRQ9
IRQ10
IRQ11
IRQ12
IRQ15
LA23–LA17
LMEG
I
DMA Channel 1 Request
DMA Channel 3 Request
DMA Channel 5 Request
DMA Channel 6 Request
DMA Channel 7 Request
DMA Channel 0 Acknowledge
DMA Channel 1 Acknowledge
DMA Channel 3 Acknowledge
DMA Channel 5 Acknowledge
DMA Channel 6 Acknowledge
DMA Channel 7 Acknowledge
Interrupt Request input
Interrupt Request input
Interrupt Request input
Interrupt Request input
Interrupt Request input
Interrupt Request input
Interrupt Request input
Interrupt Request input
ISA Non-Latched Address Bus
ISA Memory Address Decode Below 1
Mbyte
Zero Wait State
LCDD3
DSMD5
LCDD1
DSMD1
DSMD4
DSMA7
DSCE
DSMA6
LCDD0
DSMA4
DSMA5
M
CP1
DSMA1
DSMD3
CP2
DSMD2
FRM
LVEE
DSMA14–DSMA8
DSOE
174
I
170
I
175
I
166
I
169
O
158
O
146
O
159
O
144
O
161
O
160
I
173
I
178
I
164
I
168
I
179
I
167
I
181
I
182
O
149–155
O
147
0WS
I
DSMD7
172
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