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EM4469
Copyright
2003, EM Microelectronic-Marin SA
9
www.emmicroelectronic.com
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EM4469
Default Read
Preamble
Default Read
READER
"0011"
Password
Timings
T
PP
Write Word
EM4469
Default Read
Preamble
Default Read
READER
"0101"
Address
Data
Timings
T
PC
T
WEE
T
INI
Read Word
EM4469
Default Read
Preamble
Read Word
Default Read
READER
"1001" Address
Timings
T
PP
Disable
EM4469
Default Read
Disabled Mode
READER
"1010"
"all1" data
Timings
Return Link Encoder
(Tag to Reader)
As described before the NRZ data coming from
EEPROM pass in read mode (Default read or answer to
Read Word command) through Encoder before it is
transferred to Modulator. The logic 1 (high) means
Modulator is on.
Manchester Code:
In Manchester coding there is a transition from High to
Low or from Low to High in the middle of bit period.
When logic 0 is transmitted first half of bit period the
output is Low and second half of bit period it is High.
When logic 1 is transmitted first half of bit period the
output is High and second half of bit period it is Low.
Biphase Code
In Biphase coding there is a transition from High to Low
or from Low to High at the beginning of each bit period.
In the case logic 0 is transmitted there is additional
transition in the middle of bit period. In case logic 1 is
transmitted there is no transition in the middle of bit
period.
NRZ in
Manchester
Biphase
Miller Code
Advantage of Miller code is that minimum pulse duration
is one bit period. See figure below for example of Miller
code. In the case logic 1 is transmitted there is a
transition in middle of bit period. In case a single 0 is
transmitted there is no transition, in case of more zeros
there are transitions in beginning of bit period starting
with second zero.
1
1
1
1
1
0
0
0
0
0
NRZ
Miller
PSK Codes
There are two types of PSK codes implemented. The
PSK subcarrier frequency can also be defined (RF/2,
RF/4 and RF/8 are implemented). For correct operation
of PSK codes the selected data rate has to be an integer
multiple of PSK subcarrier frequency.
PSK2: Phase change on bit clock when input high
PSK3 : Phase change on rising edge of input
FSK Code:
In case logic 0 is present on the input a signal with
frequency f
RF
/5 is transmitted to output. In case logic 1 is
present on the input a signal with frequency f
RF
/8 is
transmitted to output.
Code
Logic 1
FSK
f
RF
/8
Logic 0
f
RF
/5
Examples of Settings
EM H4001, H4002, H4100 ver. 01:
Data rate:
Encoder:
LWR:
ISO11785 FDX-B
Data rate:
Encoder:
LWR:
f
RF
/64
Manchester
6 (64 bits)
f
RF
/32
Biphase
8 (128 bits)