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EM78P447S
OTP ROM
Wake-Up from Pin Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin Change
Bit Name
U
U
U
U
P
U
U
P
/WUE7 /WUE6 /WUE5 /WUE4 /WUE3 /WUE2 /WUE1 /WUE0
1
1
1
1
1
1
1
1
P
P
P
P
X
ODE
WDTE
SLPC
U
0
1
1
U
0
1
1
U
P
1
1
X
X
X
X
U
U
U
U
U
U
U
U
U
U
U
U
-
-
-
-
0
0
0
0
0
0
0
0
P
P
P
P
-
-
-
-
0x0B
0x0E
0x0F
0x08
0x09~
0x3E
IOCB
IOCE
IOCF
R8
1
1
P
1
1
P
X
U
U
U
X
U
U
U
-
0
0
P
-
1
1
P
X
U
U
U
X
U
U
U
-
0
0
P
-
1
1
P
ROC
0
0
P
EXIE
0
0
P
-
0
0
P
-
/WUE
1
1
P
TCIE
0
0
P
-
0
0
P
-
R9~R3E
Power-On
U
U
U
U
U
U
U
U
/RESET and WDT
Wake-Up from Pin Change
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
** To execute next instruction after the ”SLPC” bit status of IOCE register being on high-to-low transition.
X: Not used. U: Unknown or don’t care. -: not defined. P: Previous value before reset. t: Check Table 6
2. The Status of RST, T, and P of STATUS Register
A RESET condition is initiated by one of the following events:
1. A power-on condition,
2. A high-low-high pulse on /RESET pin, and
3. Watchdog timer time-out.
The values of T and P (listed in Table 5 below) are used to verify the event that triggered the processor to wake up.
Table 6 shows the events that may affect the status of T and P.
Table 6 The Values of RST, T and P after RESET
Reset Type
T
1
*P
1
*P
0
0
0
*P
P
1
*P
0
*P
*P
0
*P
*P
Power on
/RESET during Operating mode
/RESET wake-up during SLEEP1 mode
/RESET wake-up during SLEEP2 mode
WDT during Operating mode
WDT wake-up during SLEEP1 mode
WDT wake-up during SLEEP2 mode
Wake-Up on pin change during SLEEP2 mode
*P: Previous status before reset
This specification is subject to change without prior notice.
06.25.2003 (V1.1)
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