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EM78P451S
8-Bit Microcontroller with OTP ROM
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
43
(1). Every bit of any register can be set, cleared, or tested directly.
(2). The I/O register can be regarded as general register. That is, the same instruction
can operate on I/O register.
The symbol "R" represents a register designator that specifies which one of the
registers (including operational registers and general purpose registers) is to be utilized
by the instruction. Bits 6 and 7 in R4 determine the selected register bank. "b"
represents a bit field designator that selects the value for the bit located in the register
"R" and affects operation. "k" represents an 8 or 10-bit constant or literal value.
INSTRUCTION BINARY
HEX
MNEMONIC
OPERATION
STATUS AFFECTED
0 0000 0000 0000
0 0000 0000 0001
0 0000 0000 0010
0 0000 0000 0011
0 0000 0000 0100
0 0000 0000 rrrr
0 0000 0001 0000
0 0000 0001 0001
0 0000 0001 0010
0000
0001
0002
0003
0004
000r
0010
0011
0012
NOP
DAA
CONTW
SLEP
WDTC
IOW R
ENI
DISI
RET
No Operation
Decimal Adjust A
A
→
CONT
0
→
WDT, Stop oscillator
0
→
WDT
A
→
IOCR
Enable Interrupt
Disable Interrupt
[Top of Stack]
→
PC
[Top of Stack]
→
PC,
Enable Interrupt
CONT
→
A
IOCR
→
A
R2+A
→
R2,
Bits 8~9 of R2 unchanged
A
→
R
0
→
A
0
→
R
R-A
→
A
R-A
→
R
R-1
→
A
R-1
→
R
A
∨
VR
→
A
A
∨
VR
→
R
A & R
→
A
A & R
→
R
A
⊕
R
→
A
A
⊕
R
→
R
A + R
→
A
A + R
→
R
R
→
A
R
→
R
/R
→
A
None
C
None
T,P
T,P
None <Note1>
None
None
None
0 0000 0001 0011
0013
RETI
None
0 0000 0001 0100
0 0000 0001 rrrr
0014
001r
CONTR
IOR R
None
None <Note1>
0 0000 0010 0000
0020
TBL
Z,C,DC
0 0000 01rr rrrr
0 0000 1000 0000
0 0000 11rr rrrr
0 0001 00rr rrrr
0 0001 01rr rrrr
0 0001 10rr rrrr
0 0001 11rr rrrr
0 0010 00rr rrrr
0 0010 01rr rrrr
0 0010 10rr rrrr
0 0010 11rr rrrr
0 0011 00rr rrrr
0 0011 01rr rrrr
0 0011 10rr rrrr
0 0011 11rr rrrr
0 0100 00rr rrrr
0 0100 01rr rrrr
0 0100 10rr rrrr
00rr
0080
00rr
01rr
01rr
01rr
01rr
02rr
02rr
02rr
02rr
03rr
03rr
03rr
03rr
04rr
04rr
04rr
MOV R,A
CLRA
CLR R
SUB A,R
SUB R,A
DECA R
DEC R
OR A,R
OR R,A
AND A,R
AND R,A
XOR A,R
XOR R,A
ADD A,R
MOV A,R
MOV R,R
COMA R
None
Z
Z
Z,C,DC
Z,C,DC
Z
Z
Z
Z
Z
Z
Z
Z
Z,C,DC
Z,C,DC
Z
Z
Z