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參數(shù)資料
| 型號(hào)： | EM78P5840 |
| 廠商： | ELAN Microelctronics Corp . |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8 BIT MICROCONTROLLER |
| 中文描述： | 8位微控制器 |
| 文件頁數(shù)： | 15/48頁 |
| 文件大?。?/td> | 469K |
| 代理商： | EM78P5840 |
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EM78P5840/5841/5842
8-bit Micro-controller
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to change without notice.
2004/11/10 V2.6
R9 (PORT9 I/O data)
PAGE0 (PORT9 I/O data register)
7
6
P97
P96
R/W
R/W
Bit 0 ~ Bit 7 (P90 ~ P97) : 8-bit PORT9(0~7) I/O data register
User can use IOC register to define input or output each bit.
PAGE1:
(undefined) not allowed to use
PAGE2:
(undefined) not allowed to us
PAGE3 (DT2L: the Least Significant Byte ( Bit 7 ~ Bit 0 ) of Duty Cycle of PWM2)
7
6
5
4
PWM2[7] PWM2[6] PWM2[5] PWM2[4] PWM2[3] PWM2[2] PWM2[1] PWM2[0]
R/W-0
R/W-0
R/W-0
R/W-0
A specified value keeps the output of PWM2 to stay at high until the value matches with TMR2.
RA (PLL, Main clock selection, Watchdog timer)
PAGE0 (PLL enable bit, Main clock selection bits, Watchdog timer enable bit)
7
6
5
4
3
0
PLLEN
CLK2
CLK1
CLK0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Bit 0(WDTEN) : Watch dog control bit.
0/1
disable/enable
User can use WDTC instruction to clear watch dog counter. The watchdog timer is a free running on-chip RC
oscillator. The WDT will keep on running even after the oscillator driver has been turned off (i.e. in sleep mode).
During normal operation or sleep mode, a WDT time-out (if enabled) will cause the device to reset. The WDT can
be enabled or disabled at any time during the green mode or normal mode by software programming. Without
presacler, the WDT time-out period is approximately 18 ms.
Bit 1~Bit 2 : Unused
Bit 3 ~ Bit 5 (CLK0 ~ CLK2) : MAIN clock selection bits on Crystal mode. These three bits are unused on
IRC and ERIC mode.
In Crystal mode:
User can choose different frequency of main clock by CLK1 and CLK2. All the clock selection is list below.
PLLEN
CLK2
CLK1
CLK0
Sub clock
1
0
0
0
32.768kHz
1
0
0
1
32.768kHz
1
0
1
0
32.768kHz
1
0
1
1
32.768kHz
1
1
0
0
32.768kHz
1
1
0
1
32.768kHz
1
1
1
0
32.768kHz
1
1
1
1
32.768kHz
0
don’t care don’t care don’t care
32.768kHz
Bit 6(PLLEN) : PLL's power control bit which is CPU mode control register. This bit is only used in crystal
mode. In RC mode, this bit will be ignored.
0/1
disable PLL/enable PLL
5
4
3
2
1
0
P95
R/W
P94
R/W
P93
R/W
P92
R/W
P91
R/W
P90
R/W
3
2
1
0
R/W-0
R/W-0
R/W-0
R/W-0
2
X
-
1
X
-
0
WDTEN
R/W-0
MAIN clock
3.582MHz
3.582MHz
3.582MHz
3.582MHz
14.3MHz
14.3MHz
14.3MHz
14.3MHz
don’t care
CPU clock
3.582MHz (Normal mode)
3.582MHz (Normal mode)
3.582MHz (Normal mode)
3.582MHz (Normal mode)
14.3MHz (Normal mode)
14.3MHz (Normal mode)
14.3MHz (Normal mode)
14.3MHz (Normal mode)
32.768kHz (Green mode)
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