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參數(shù)資料
| 型號(hào)： | EM78P5841 |
| 廠商： | ELAN Microelctronics Corp . |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8 BIT MICROCONTROLLER |
| 中文描述： | 8位微控制器 |
| 文件頁數(shù)： | 11/48頁 |
| 文件大?。?/td> | 469K |
| 代理商： | EM78P5841 |
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EM78P5840/5841/5842
8-bit Micro-controller
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to change without notice.
2004/11/10 V2.6
"ADD R2,A" allows a relative address be added to the current PC, and contents of the ninth and tenth bits are
cleared to "0''.
"TBL" allows a relative address added to the current PC, and contents of the ninth and tenth bits don't change.
The most significant bit (A10~A11) will be loaded with the contents of bit PS0~PS1 in the status register (R5
PAGE0) upon the execution of a "JMP'', "CALL'', "ADD R2, A'', or "MOV R2, A'' instruction.
If an interrupt is triggered, PROGRAM ROM will jump to address 0x08 at page0. The CPU will store ACC,
R3 status and R5 PAGE automatically, and they will be restored after instruction RETI.
A11 A10 A9 A8 A7~A0
0 0
PAGE0 00000~003FF
0 1
PAGE1 00400~007FF
1 0
PAGE2 00800~00BFF
STACK1
STACK2
STACK3
STACK5
STACK6
STACK7
STACK4
STACK8
CALL
and
INTERRUPT
RET
RETL
RETI
ACC,R3,R5(PAGE)
R5(PAGE)
store
restore
1 1
PAGE3 00C00~00FFF
Fig.3 Program counter organization
R3 (Status, Page selection)
(Status flag, Page selection bits)
7
RPAGE1
RPAGE0
R/W-0
R/W-0
Bit 0(C) : Carry flag
Bit 1(DC) : Auxiliary carry flag
Bit 2(Z) : Zero flag
Bit 3(P) : Power down bit
Set to 1 during power on or by a "WDTC" command and reset to 0 by a "SLEP" command.
Bit 4(T) : Time-out bit
Set to 1 by the "SLEP" and "WDTC" command, or during power up and reset to 0 by WDT timeout.
6
5
4
T
R
3
P
R
2
Z
1
0
C
IOCPAGE
R/W-0
DC
R/W
R/W
R/W
EVENT
T
P
REMARK
WDT wake up from sleep mode
WDT time out (not sleep mode)
/RESET wake up from sleep
Power up
Low pulse on /RESET
Bit 5(IOCPAGE) : change IOC5 ~ IOCE to another page
Please refer to Fig.4 control register configuration for details.
0/1
IOC page0 / IOC page1
Bit 6(RPAGE0 ~ RPAGE1) : change R5 ~ RE to another page
Please refer to VII.1 Operational registers for detail register configuration.
0
0
1
1
x
0
1
0
1
X
x : don't care
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