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參數(shù)資料
| 型號(hào)： | EM78P860 |
| 廠商： | ELAN Microelctronics Corp . |
| 英文描述： | 8 -BIT MICRO-CONTROLLER |
| 中文描述： | 8位微控制器 |
| 文件頁(yè)數(shù)： | 16/26頁(yè) |
| 文件大?。?/td> | 191K |
| 代理商： | EM78P860 |
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EM78P860
8 -BIT MICRO-CONTROLLER
* This specification is subect tobechanged wthout noice
4.17.2000
16
It is very important to save ACC,R3 and R5 when processing a interruption.
Address
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
:
:
:
:
:
:
:
:
Instruction
DISI
MOV A_BUFFER,A
SWAP A_BUFFER
SWAPA 0x03
MOV R3_BUFFER,A
MOV A,0x05
MOV R5_BUFFER,A
:
:
MOV A,R5_BUFFER
MOV 0X05,A
SWAPA R3_BUFFER
MOV 0X03,A
SWAPA A_BUFFER
RETI
Note
;Disable interrupt
;Save ACC
;Save R3 status
;Save ROM page register
;Return R5
;Return R3
;Return ACC
VII.7 Instruction Set
Instruction set has the following features:
(1)
Every bit of any register can be set, cleared, or tested directly.
(2)
The I/O register can be regarded as general register. That is, the same instruction can operates on I/O register.
The symbol “R” represents a register designator which specifies which one of the 64 registers (including
operational registers and general purpose registers) is to be utilized by the instruction. Bits 6 and 7 in R4
determine the selected register bank. “b’’ represents a bit field designator which selects the number of the
bit, located in the register “R’’, affected by the operation. “k’’ represents an 8 or 10-bit constant or literal
value.
INSTRUCTION
BINARY
0 0000 0000 0000
0 0000 0000 0001
0 0000 0000 0010
0 0000 0000 0011
0 0000 0000 0100
0 0000 0000 rrrr
STATUS
AFFECTED
None
C
None
T,P
T,P
None
<Note1>
None
None
None
None
HEX
0000
0001
0002
0003
0004
000r
MNEMONIC
NOP
DAA
CONTW
SLEP
WDTC
IOW R
OPERATION
No Operation
Decimal Adjust A
A
→
CONT
0
→
WDT, Stop oscillator
0
→
WDT
A
→
IOCR
0 0000 0001 0000
0 0000 0001 0001
0 0000 0001 0010
0 0000 0001 0011
0010
0011
0012
0013
ENI
DISI
RET
RETI
Enable Interrupt
Disable Interrupt
[Top of Stack] PC
[Top of Stack] PC
Enable Interrupt
CONT
→
A
IOCR
→
A
0 0000 0001 0100
0 0000 0001 rrrr
0014
001r
CONTR
IOR R
None
None
<Note1>
Z,C,DC
None
Z
Z
0 0000 0010 0000
0 0000 01rr rrrr
0 0000 1000 0000
0 0000 11rr rrrr
0020
00rr
0080
00rr
TBL
MOV R,A
CLRA
CLR R
R2+A Bits 8~9 of R2 unchange
A
→
R
0
→
A
0
→
R
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