參數(shù)資料
型號: EM92547D
廠商: ELAN Microelctronics Corp .
英文描述: CALLER ID FSK DECODER
中文描述: 來電顯示FSK信號解碼器
文件頁數(shù): 5/13頁
文件大小: 136K
代理商: EM92547D
EM92547A/B/D
CALLER ID FSK DECODER
________________________________________________________________________________________________________________________________________________________
* This specification are subject to be changed without notice.
1998
~ 4 ~
A /PWR UP input pin is provided to activate the chip regardless of the presence of a
power ring signal. If /PWR UP is sent high, the IC can still power itself up whenever it
detects a valid ring signal, but will back to its normal power-down mode after a time period.
The input buffer accepts a differential AC coupled input signal through the TIP and
RING input and feeds this signal to a band pass filter. Once the signal is filtered, the FSK
demodulator decodes the information and sents it to a post filter. The output data is then
made available at DATA OUT pin. This data, as sent by the central office, includes the
header information (alternate "1" and "0") and 150msec of marking which precedes the date,
time and calling number. If no data is present, the DATA OUT pin is held in a low state.
This is accomplished by a carrier detect circuit which determines if the in-band energy is
high enough. If the incoming signal is valid and thus the demodulated data is transferred to
DATA OUT pin. If it is not, then the FSK demodulator is blocked. This device uses a 3.58
MHz crystal or a 455KHz(for EM92547A only) resonator as a timing source for all the
internal blocks.
* Ring detect circuit
When Vdd is applied to the circuit, the RC network will charge cap C1 to Vdd
holding /RING TIME off. If /PWRUP is also held at Vdd, the whole circuit will be in a
power down mode, and will consume less than 1uA of supply current. The resistor network
R2 to R4 attenuates the incoming power ring applied to the top of R2. The values given
have been chosen to provide a sufficient voltage at pin3, to turn on the Schmitt trigger input.
When Vt+ of the Schmitt is exceeded, cap C1 will discharge. This will initialize a partial
power up, and enable the ring detect circuit.
The value of R1 and C1 must be chosen to hold the /RING TIME pin voltage below
the Vt+ of the Schmitt between the individual cycle of the power ring. The values shown
will work for ring frequencies of 15.3 Hz minimum.
/PWR UP
VDD
/Ring Time
C1
Ring det1
Ring det2
1.2V
Ring
Counter
Power Up
Logic
R3
R4
R1
R2
/RD
(form bridge)
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