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Point of Sale Terminal Design Guide
Application Note
9
The design’s application flash memory consists of one Intel 28F320S5 from the Word-Wide
FlashFile Memory Family. This 16-bit, word-wide FlashFile memory provides high-density,
low-cost, nonvolatile, read/write storage solutions for a wide range of applications. Key
enhancements include:
Common Flash Interface (CFI) support
Scalable Command Set (SCS) support
S5 technology
Enhanced suspend capabilities
2.2.5
Serial and Parallel Ports
There are four serial ports in the POS terminal design. COM1 and COM2 are generated and
supported by the National Semiconductor 87307 Super I/O device. COM3 and COM4 are
generated and controlled by the Exar ST16C452* Dual Asynchronous Receiver/Transmitter.
GD 75232* drivers/receivers from Texas Instruments provide the interface between the UART and
the communication ports. This device provides a low-cost solution for this function and allows
easy interconnection of the UART and communication ports. It also complies with the
requirements of the EIA/TIA-232-E and ITU standards.
The parallel port on the POS terminal design is generated and controlled by the National
Semiconductor 87307 Super I/O device. The parallel port uses a DB25 connector.
2.2.6
IDE Port
Two standard IDE interfaces are provided by the 82371SB. One 40-pin IDE connector is included
in the design. This allows up to two IDE devices (one master and one slave) to be supported in a
single connector.
2.2.7
PCMCIA Interface
The Cirrus Logic CL-PD6720* is used as the host adapter chip to control two PCMCIA sockets.
Only one socket is implemented in this design. The chip is fully PCMCIA (v2.1) and JEIDA (v4.1)
compliant. The CL-PD6720 provides fully buffered PCMCIA interfaces. No external logic is
required for buffering signals to or from the interface. Power consumption can be controlled by
limiting signal transitions on the PCMCIA bus.
2.2.8
PS/2 Mouse Port
A PS/2-type mouse port is provided by the National Semiconductor 87307 Super I/O device.