參數(shù)資料
型號: EN29LV640L-90TI
廠商: Eon Silicon Solution Inc.
英文描述: 64 Megabit (4M x 16-bit ) CMOS 3.0 Volt-only, Uniform Sector Flash Memory
中文描述: 64兆位(4米× 16位),3.0伏的CMOS只,統(tǒng)一部門快閃記憶體
文件頁數(shù): 17/45頁
文件大?。?/td> 440K
代理商: EN29LV640L-90TI
Hardware Data protection
The command sequence requirement of unlock cycles for programming or erasing provides data
protection against inadvertent writes as seen in the Command Definitions table. Additionally, the
following hardware data protection measures prevent accidental erasure or programming, which
might otherwise be caused by false system level signals during Vcc power up and power down
transitions, or from system noise.
Low V
B
CC
When V
CC
is less than V
B
LKO
V
CC
power up and power down. The command register and all internal program/erase circuits are
disabled, and the device resets. Subsequent writes are ignored until V
CC
is greater than V
B
LKO
system must provide the proper signals to the control pins to prevent unintentional writes when V
CC
is greater than V
B
LKO
Write Pulse “Glitch” protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = V
B
IL
write cycle, CE# and WE# must be a logical zero while OE# is a logical one. If CE#, WE#, and OE#
are all logical zero (not recommended usage), it will be considered a read.
Power-up Write Inhibit
During power-up, the device automatically resets to READ mode and locks out write cycles. Even
with CE# = V
B
IL
WE#.
This Data Sheet may be revised by subsequent versions 2005 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.
Rev. C, Issue Date: 2007/01/23
EN29LV640
B
Write Inhibit
B
, the device does not accept any write cycles. This protects data during
B
. The
B
.
B
, CE# = V
B
IH
B
, or WE# = V
B
IH
B
. To initiate a
B
, WE#= V
B
IL
B
and OE# = V
B
IH
B
, the device will not accept commands on the rising edge of
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