參數(shù)資料
型號: EN29LV800B70RTIP
廠商: Electronic Theatre Controls, Inc.
英文描述: 8 Megabit (1024K x 8-bit / 512K x 16-bit) Flash Memory Boot Sector Flash Memory, CMOS 3.0 Volt-only
中文描述: 8兆位(1024K × 8位/為512k × 16位)閃存引導(dǎo)扇區(qū)閃存,CMOS 3.0伏,只
文件頁數(shù): 14/43頁
文件大小: 239K
代理商: EN29LV800B70RTIP
EN29LV800
4800 Great America Parkway, Suite 202
Santa Clara, CA 95054
Tel: 408-235-8680
Fax: 408-235-8685
14
Rev 0.4 Release Date: 2002/01/29
The system must write the Erase Resume command (address bits are don’t-care) to exit the erase
suspend mode and continue the sector erase operation. Further writes of the Resume command are
ignored. Another Erase Suspend command can be written after the device has resumed erasing.
WRITE OPERATION STATUS
DQ7:
DATA
Polling
The EN29LV800 provides
DATA
Polling on DQ7 to indicate to the host system the status of the
embedded operations. The
DATA
Polling feature is active during the Byte Programming, Sector
Erase, Chip Erase, Erase Suspend. (See Table 6)
When the Byte Programming is in progress, an attempt to read the device will produce the
complement of the data last written to DQ7. Upon the completion of the Byte Programming, an
attempt to read the device will produce the true data last written to DQ7. For the Byte Programming,
DATA
polling is valid after the rising edge of the fourth
WE
or
CE
pulse in the four-cycle sequence.
When the embedded Erase is in progress, an attempt to read the device will produce a “0” at the
DQ7 output. Upon the completion of the embedded Erase, the device will produce the “1” at the DQ7
output during the read. For Chip Erase, the
DATA
polling is valid after the rising edge of the sixth
W E
or
CE
pulse in the six-cycle sequence. For Sector Erase,
DATA
polling is valid after the last
rising edge of the sector erase
W E
or
CE
pulse.
DATA
Polling must be performed at any address within a sector that is being programmed or erased
and not a protected sector. Otherwise,
DATA
polling may give an inaccurate result if the address
used is in a protected sector.
Just prior to the completion of the embedded operations, DQ7 may change asynchronously when the
output enable (
OE
) is low. This means that the device is driving status information on DQ7 at one
instant of time and valid data at the next instant of time. Depending on when the system samples the
DQ7 output, it may read the status of valid data. Even if the device has completed the embedded
operations and DQ7 has a valid data, the data output on DQ0-DQ6 may be still invalid. The valid
data on DQ0-DQ7 will be read on the subsequent read attempts.
The flowchart for
DATA
Polling (DQ7) is shown on Flowchart 5. The
DATA
Polling (DQ7) timing
diagram is shown in Figure 8.
RY/BY: Ready/Busy
The RY/BY is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY status is valid after the rising edge of the final WE pulse in the
command sequence. Since RY/BY is an open-drain output, several RY/BY pins can be tied together
in parallel with a pull-up resistor to Vcc.
In the output is low, signifying Busy, the device is actively erasing or programming. This includes
programming in the Erase Suspend mode. If the output is high, signifying the Ready, the device is
ready to read array data (including during the Erase Suspend mode), or is in the standby mode.
DQ6: Toggle Bit I
The EN29LV800 provides a “Toggle Bit” on DQ6 to indicate to the host system the status of the
embedded programming and erase operations. (See Table 6)
相關(guān)PDF資料
PDF描述
EN29LV800 Replaced by PTH04070W :
EN29LV800B70RS Replaced by PTH04070W :
EN29LV800B70RSI Replaced by PTH04070W :
EN29LV800B70RSP 8 Megabit (1024K x 8-bit / 512K x 16-bit) Flash Memory Boot Sector Flash Memory, CMOS 3.0 Volt-only
EN29LV800B70RT 8 Megabit (1024K x 8-bit / 512K x 16-bit) Flash Memory Boot Sector Flash Memory, CMOS 3.0 Volt-only
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