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參數(shù)資料
| 型號： | ENC28J60T-I/SO |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 6/12頁 |
| 文件大小： | 0K |
| 描述： | IC ETHERNET CTRLR W/SPI 28-SOIC |
| 標準包裝： | 1,600 |
| 控制器類型： | 以太網(wǎng)控制器，MAC/10Base-T |
| 接口： | SPI |
| 電源電壓： | 3.1 V ~ 3.6 V |
| 電流 - 電源： | 160mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 28-SOIC |
| 包裝： | 帶卷 (TR) |
| 產(chǎn)品目錄頁面： | 684 (CN2011-ZH PDF) |
| 配用： | DM163024-ND - BOARD DEMO PICDEM.NET 2 AC164123-ND - BOARD DAUGHTER ETH PICTAIL PLUS AC164121-ND - BOARD DAUGHTER PICTAIL ETHERNET |
| 其它名稱： | ENC28J60T-I/SO-ND ENC28J60T-I/SOTR |
2010 Microchip Technology Inc.
DS80349C-page 3
ENC28J60
Silicon Errata Issues
1. Module: MAC Interface
When the SPI clock from the host microcontroller
is run at frequencies of less than 8 MHz, reading or
writing to the MAC registers may be unreliable.
Work around
Two work arounds are presented; others may be
available.
1. Run the SPI at frequencies of at least 8 MHz.
2. Generate an SPI clock of 25/2 (12.5 MHz),
25/3 (8.333
MHz),
25/4
(6.25
MHz),
25/5 (5 MHz), etc., and synchronize with the
25 MHz clock entering OSC1 on the
ENC28J60. This could potentially be accom-
plished by feeding the same 25 MHz clock into
the ENC28J60 and host controller. Alterna-
tively, the host controller could potentially be
clocked off of the CLKOUT output of the
ENC28J60.
Affected Silicon Revisions
2. Module: Reset
After sending an SPI Reset command, the PHY
clock is stopped but the ESTAT.CLKRDY bit is not
cleared. Therefore, polling the CLKRDY bit will not
work to detect if the PHY is ready.
Additionally, the hardware start-up time of 300
s
may expire before the device is ready to operate.
Work around
After issuing the Reset command, wait at least
1 ms in firmware for the device to be ready.
Affected Silicon Revisions
3. Module: Core (Operating Specifications)
The device data sheet specifies that industrial
operating temperature range (-40
C to +85C) is
supported. However, silicon revisions B1 and B4
only support the commercial temperature range
(0
C to +70C).
Work around
Use silicon revision B5 or later.
Affected Silicon Revisions
4. Module: Oscillator (CLKOUT Pin)
No output is available on CLKOUT while operating
in Power Save mode (ECON2.PWRSV = 0).
Work around
If the host controller uses the CLKOUT signal as
the system clock, do not enable Power Save
mode.
Affected Silicon Revisions
5. Module: Memory (Ethernet Buffer)
The receive hardware maintains an internal Write
Pointer which defines the area in the receive buffer
where bytes arriving over the Ethernet are written.
This internal Write Pointer should be updated with
the value stored in ERXST whenever the Receive
Buffer Start Pointer, ERXST, or the Receive Buffer
End Pointer, ERXND, is written to by the host
microcontroller. Sometimes, when ERXST or
ERXND is written to, the exact value, 0000h, is
stored in the internal receive Write Pointer instead
of the ERXST address.
Work around
Use the lower segment of the buffer memory for
the receive buffer, starting at address 0000h. For
example, use the range (0000h to n) for the
receive buffer and ((n + 1) to 8191) for the transmit
buffer.
Affected Silicon Revisions
Note:
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (B7).
B1
B4
B5
B7
XX
B1
B4
B5
B7
XX
X
B1
B4
B5
B7
XX
B1
B4
B5
B7
XX
X
B1
B4
B5
B7
XX
X
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