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參數(shù)資料
| 型號(hào)： | ENC28J60T/SO |
| 廠商： | Microchip Technology |
| 文件頁(yè)數(shù)： | 7/12頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ETHERNET CTRLR W/SPI 28SOIC |
| 標(biāo)準(zhǔn)包裝： | 1,600 |
| 控制器類(lèi)型： | 以太網(wǎng)控制器，MAC/10Base-T |
| 接口： | SPI |
| 電源電壓： | 3.1 V ~ 3.6 V |
| 電流 - 電源： | 160mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SOIC |
| 包裝： | 帶卷 (TR) |
| 配用： | DM163024-ND - BOARD DEMO PICDEM.NET 2 AC164123-ND - BOARD DAUGHTER ETH PICTAIL PLUS AC164121-ND - BOARD DAUGHTER PICTAIL ETHERNET |
ENC28J60
DS80349C-page 4
2010 Microchip Technology Inc.
6. Module: Interrupts
The Receive Packet Pending Interrupt Flag
(EIR.PKTIF) does not reliably/accurately report
the status of pending packets.
Work around
In the Interrupt Service Routine (ISR), if it is
unknown if a packet is pending and the source of
the interrupt, switch to Bank 1 and check the value
in EPKTCNT.
If polling to see if a packet is pending, check the
value in EPKTCNT.
Affected Silicon Revisions
7. Module: PHY
The automatic RX polarity detection and correc-
tion features of the PHY layer do not work as
described. When incorrect RX polarity is present,
poor receive network performance, or no receive
activity with some link partners, may occur.
Work around
When designing the application, always verify that
the TPIN+ and TPIN- pins are connected correctly.
Affected Silicon Revisions
8. Module: PHY
The external resistor value recommended for
RBIAS in the current revision of the data sheet does
not apply to certain revisions of silicon. Using an
incorrect resistor value will cause the Ethernet trans-
mit waveform to violate IEEE 802.3 specification
requirements.
Work around
For silicon revisions, B1 and B4, use a 2.7 k
, 1%
external resistor between the RBIAS pin and
ground. The value shown in the data sheet
(2.32 k
,) is correct for revisions B5 and B7.
Affected Silicon Revisions
9. Module: PHY
The PHY Half-Duplex Loopback mode, enabled when
PHCON1.PDPXMD = 0, PHCON2.HDLDIS = 0 and
PHCON2.FRCLNK = 1, or a link partner is connected,
does not loop packets back to itself reliably.
Work around
Perform loopback diagnostics in full duplex using
an external loopback connector/cable. To avoid
looping occasional packets back to one self,
PHCON2.HDLDIS should be set by the host
controller. PHCON2.HDLDIS is clear by default.
Affected Silicon Revisions
10. Module: PHY
The
PHY
Full-Duplex
Loopback
mode,
enabled when PHCON1.PDPXMD = 1 and
PHCON1.PLOOPBK = 1, does not loop packets
back to itself reliably.
Work around
Perform loopback diagnostics in full duplex using
an external loopback connector/cable.
Affected Silicon Revisions
Note:
This errata applies only to the interrupt
flag. If the receive packet pending interrupt
is enabled, the INT pin will continue to
reliably become asserted when a packet
arrives. The receive packet pending inter-
rupt is cleared in the same manner
described in the data sheet.
B1
B4
B5
B7
XX
X
B1
B4
B5
B7
XX
X
B1
B4
B5
B7
XX
B1
B4
B5
B7
XX
X
B1
B4
B5
B7
XX
X
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