- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄97896 > ENH104V2-380 LDO with Low ISUPPLY, High PSRR; Temperature Range: -40°C to 85°C; Package: 8-DFN T&R PDF資料下載
參數(shù)資料
| 型號： | ENH104V2-380 |
| 英文描述： | LDO with Low ISUPPLY, High PSRR; Temperature Range: -40°C to 85°C; Package: 8-DFN T&R |
| 中文描述： | 10.4英寸顯卡 |
| 文件頁數(shù)： | 13/16頁 |
| 文件大小： | 209K |
| 代理商： | ENH104V2-380 |
Original specifications created by Sharp.
6
Panelview Hillsboro, OR (503) 690-2460
Panelview is a subsidiary of White Electronic Designs Corporation
ENH104V1-350/450
Panelview
Enhancing the Vision
TIMING CHARACTERISTICS OF INPUT SIGNALS
Timing diagrams of input signal are shown in Fig.2 - (1)~(3).
TIMING CHARACTERISTICS
Parameter
Symbol
Mode
Min.
Typ.
Max.
Unit
Clock
Frequency
1/Tc
all
-
25.1828
.33
MHz
High time
Tch
all
5
-
ns
Low time
Tcl
all
10
-
ns
Data
Setup time
Tds
all
5
-
ns
Hold time
Tdh
all
10
-
ns
Horizontal
Cycle
TH
all
30.00
31.78-
s
sync. signal
all
750
800
900
clock
Pulse width
THp
all
2
96
200
clock
Vertical
Cycle
TV
480
515
525
560
line
sync. signal
400
446
449
480
line
350
447
449
510
line
Pulse width
TVp
all
1
-
34
line
Horizontal display period
THd
all
640
clock
Hsync-Clock
THc
all
10
-
TC-10
ns
phase difference
Hsync-Vsync
TVh
all
0
-
TH-THp
clock
phase difference
Note: In case of lower frequency, the deterioration of display quality, flicker, etc., may occur.
Horizontal Display Position
The horizontal display position is determined by ENAB signal and the input data corresponding to the rising edge
of ENAB signal is displayed at the left end of the active area.
Parameter
Symbol
Min.
Typ.
Max.
Unit
Enable signal
Setup time
Tes
5
-
Tc-10
ns
Pulse width
Tep
2
640
clock
Hsync-Enable signal
THe
44
-
TH-664
clock
phase difference
Note: When ENAB is fixed Low, the display starts from the data of C104 (clock) as shown in Fig.2 - (1)~(3). Be careful that
the module does not work when ENAB is fixed High. When the phase difference is below 104 clock, keep the High level of
ENAB signal longer than 104-The. If it is not kept, the display starts from the data of C104 (clock).
相關PDF資料 |
PDF描述 |
|---|---|
| ENH104V2-450 | LDO with Low ISUPPLY, High PSRR; Temperature Range: -40°C to 85°C; Package: 8-DFN T&R |
| ENH104V2-600 | LDO with Low ISUPPLY, High PSRR; Temperature Range: -40°C to 85°C; Package: 8-DFN T&R |
| EIMR_12_SCH | eIMR Reference Design Schematics (12 Port)? 413KB (PDF) |
| EIMR_4_SCH | 3.3V Half Duplex, 20Mbps, IEC61000 ESD Protected, RS-485/RS-422 Transceiver; Temperature Range: -40°C to 85°C; Package: 8-SOIC |
| EIMR_8_PORT | 3.3V Half Duplex, 20Mbps, IEC61000 ESD Protected, RS-485/RS-422 Transceiver; Temperature Range: -40°C to 85°C; Package: 8-MSOP |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ENH104V2-450 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:Color TFT-LCD Module Features |
| ENH104V2-600 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:Color TFT-LCD Module Features |
| ENH104V2-XXX | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:Color TFT-LCD Module Features |
| ENH121S1-250 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:12.1inch SVGA |
| ENH121S1-350 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:12.1inch SVGA |
發(fā)布緊急采購，3分鐘左右您將得到回復。