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參數(shù)資料
| 型號(hào)： | EP1AGX35DF780C6N |
| 廠商： | Altera |
| 文件頁(yè)數(shù)： | 3/4頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ARRIA GX FPGA 35K 780FBGA |
| 產(chǎn)品培訓(xùn)模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標(biāo)準(zhǔn)包裝： | 12 |
| 系列： | Arria GX |
| LAB/CLB數(shù)： | 1676 |
| 邏輯元件/單元數(shù)： | 33520 |
| RAM 位總計(jì)： | 1348416 |
| 輸入/輸出數(shù)： | 341 |
| 電源電壓： | 1.15 V ~ 1.25 V |
| 安裝類(lèi)型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 780-BBGA |
| 供應(yīng)商設(shè)備封裝： | 780-FBGA（29x29） |
| 其它名稱(chēng)： | 544-2374 |
Chapter 1: Arria GX Device Family Overview
1–3
Features
December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
Arria GX devices are available in space-saving FBGA packages (refer to Table 1–2). All
Arria GX devices support vertical migration within the same package. With vertical
migration support, designers can migrate to devices whose dedicated pins,
configuration pins, and power pins are the same for a given package across device
densities. For I/O pin migration across densities, the designer must cross-reference
the available I/O pins with the device pin-outs for all planned densities of a given
package type to identify which I/O pins are migratable.
Source-
synchronous
transmit
channels
29
29, 42
29
42
45
M512 RAM
blocks
(32 × 18 bits)
166
197
313
326
478
M4K RAM
blocks
(128 × 36
bits)
118
140
242
252
400
M-RAM
blocks
(4096 × 144
bits)
11
2
4
Total RAM
bits
1,229,184
1,348,416
2,475,072
2,528,640
4,477,824
Embedded
multipliers
(18 × 18)
40
56
104
128
176
DSP blocks
10
14
26
32
44
PLLs
4
4, 8
4
8
Maximum
user I/O pins
230, 341
230
341
229
350, 514
229
350
514
538
Table 1–1. Arria GX Device Features (Part 2 of 2)
Feature
EP1AGX20C
EP1AGX35C/D
EP1AGX50C/D
EP1AGX60C/D/E
EP1AGX90E
C
CDC
D
C
D
E
Table 1–2. Arria GX Package Options (Pin Counts and Transceiver Channels) (Part 1 of 2)
Device
Transceiver
Channels
Source-Synchronous Channels
Maximum User I/O Pin Count
Receive
Transmit
484-Pin FBGA
(23 mm)
780-Pin FBGA
(29 mm)
1152-Pin
FBGA
(35 mm)
EP1AGX20C
4
31
29
230
341
—
EP1AGX35C
4
31
29
230
—
EP1AGX50C
4
31
29
229
—
EP1AGX60C
4
31
29
229
—
EP1AGX35D
8
31
29
—
341
—
EP1AGX50D
8
31, 42
29, 42
—
350
514
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP1AGX35DF780I6 | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 FPGA - Arria GX 1676 LABs 341 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP1AGX35DF780I6N | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 FPGA - Arria GX 1676 LABs 341 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP1AGX35EF1152C6N | 制造商:ALTERA 制造商全稱(chēng):Altera Corporation 功能描述:Section I. Arria GX Device Data Sheet |
| EP1AGX35EF1152I6N | 制造商:ALTERA 制造商全稱(chēng):Altera Corporation 功能描述:Section I. Arria GX Device Data Sheet |
| EP1AGX35EF484C6N | 制造商:ALTERA 制造商全稱(chēng):Altera Corporation 功能描述:The ArriaTM GX family of devices combines 3.125 gigabits per second (Gbps) serial transceivers |
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