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參數(shù)資料
| 型號： | EP1AGX50DF1152C6N |
| 廠商： | Altera |
| 文件頁數(shù)： | 2/4頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ARRIA GX FPGA 50K 1152FBGA |
| 產(chǎn)品培訓(xùn)模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標(biāo)準(zhǔn)包裝： | 12 |
| 系列： | Arria GX |
| LAB/CLB數(shù)： | 2508 |
| 邏輯元件/單元數(shù)： | 50160 |
| RAM 位總計： | 2475072 |
| 輸入/輸出數(shù)： | 514 |
| 電源電壓： | 1.15 V ~ 1.25 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 1152-BBGA |
| 供應(yīng)商設(shè)備封裝： | 1152-FBGA（27x27） |
| 其它名稱： | 544-2376 |
1–2
Chapter 1: Arria GX Device Family Overview
Features
Arria GX Device Handbook, Volume 1
December 2009
Altera Corporation
■
Main device features:
■
TriMatrix memory consisting of three RAM block sizes to implement true
dual-port memory and first-in first-out (FIFO) buffers with performance up to
380 MHz
■
Up to 16 global clock networks with up to 32 regional clock networks per
device
■
High-speed DSP blocks provide dedicated implementation of multipliers,
multiply-accumulate functions, and finite impulse response (FIR) filters
■
Up to four enhanced phase-locked loops (PLLs) per device provide spread
spectrum, programmable bandwidth, clock switch-over, and advanced
multiplication and phase shifting
■
Support for numerous single-ended and differential I/O standards
■
High-speed source-synchronous differential I/O support on up to 47 channels
■
Support for source-synchronous bus standards, including SPI-4 Phase 2
(POS-PHY Level 4), SFI-4.1, XSBI, UTOPIA IV, NPSI, and CSIX-L1
■
Support for high-speed external memory including DDR and DDR2 SDRAM,
and SDR SDRAM
■
Support for multiple intellectual property megafunctions from Altera
MegaCore functions and Altera Megafunction Partners Program (AMPPSM)
■
Support for remote configuration updates
Table 1–1 lists Arria GX device features for FineLine BGA (FBGA) with flip chip
packages.
Table 1–1. Arria GX Device Features (Part 1 of 2)
Feature
EP1AGX20C
EP1AGX35C/D
EP1AGX50C/D
EP1AGX60C/D/E
EP1AGX90E
C
CDC
D
C
D
E
Package
484-pin,
780-pin
(Flip chip)
484-pin
(Flip chip)
780-pin
(Flip chip)
484-pin
(Flip chip)
780-pin,
1152-pin
(Flip chip)
484-pin
(Flip chip)
780-pin
(Flip chip)
1152-pin
(Flip chip)
1152-pin
(Flip chip)
ALMs
8,632
13,408
20,064
24,040
36,088
Equivalent
logic
elements
(LEs)
21,580
33,520
50,160
60,100
90,220
Transceiver
channels
4
848
4
8
12
Transceiver
data rate
600 Mbps
to 3.125
Gbps
600 Mbps to 3.125
Gbps
600 Mbps to 3.125
Gbps
600 Mbps to 3.125 Gbps
600 Mbps
to 3.125
Gbps
Source-
synchronous
receive
channels
31
31, 42
31
42
47
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP1AGX50DF1152I6N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Arria GX 2508 LABs 514 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP1AGX50DF484C6N | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:The ArriaTM GX family of devices combines 3.125 gigabits per second (Gbps) serial transceivers |
| EP1AGX50DF484I6N | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Section I. Arria GX Device Data Sheet |
| EP1AGX50DF780C6 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Arria GX 2508 LABs 350 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP1AGX50DF780C6N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Arria GX 2508 LABs 350 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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