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參數(shù)資料
| 型號： | EP1C3T100A8N |
| 廠商： | Altera |
| 文件頁數(shù)： | 43/78頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CYCLONE FPGA 2910 LE 100-TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標準包裝： | 180 |
| 系列： | Cyclone® |
| LAB/CLB數(shù)： | 291 |
| 邏輯元件/單元數(shù)： | 2910 |
| RAM 位總計： | 59904 |
| 輸入/輸出數(shù)： | 65 |
| 電源電壓： | 1.425 V ~ 1.575 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 100-TQFP |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP（14x14） |
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7–2
Chapter 7: HardCopy II Devices
Quartus II Software Support
Altera Corporation
Quartus II Software Support
The Altera Quartus II design software supports the HardCopy II devices in the
automotive temperature range. The Quartus II software provides a comprehensive
environment for system on a chip (SoC) design. It also includes HDL and schematic
design entry, compilation and logic synthesis, full simulation and advanced timing
analysis, SignalTap II logic analyzer, and device configuration.
f For more information about using the Quartus II software for the HardCopy II
development flow and settings, refer to the Quartus II Support for HardCopy II Devices
chapter in volume 1 of the HardCopy II Device Handbook.
To target an automotive-grade HardCopy II device in your design in the Quartus II
software, follow these steps:
1. On the Assignments menu, click Device. The Settings dialog box appears.
2. In the Family drop-down list, select HardCopy II.
3. Under Target device, select Specific device selected in ‘Available devices’ list.
4. In the Available devices list, select the appropriate ordering code, as listed in
5. Click OK.
1 Support for the automotive-grade HardCopy II devices is only available in the
Quartus II software version 7.2 SP1 and later.
Power Analysis and Estimation
Altera provides the following power analysis and estimation tools for your design:
■
■
PowerPlay Early Power Estimator
The PowerPlay Early Power Estimator (EPE) is a power estimation tool that helps you
estimate the power consumption of your design during the system planning phase for
proper power supply planning and consideration. The EPE allows you to enter design
information based on architectural features and calculates the power consumed by
each architectural feature. Inputs to the EPE are environmental conditions and device
resources (such as clock frequency) that you expect to use in your design. The EPE
then calculates the static and dynamic power, current estimates, and thermal analysis
for your design.
You can either enter the design information manually into the spreadsheet or import a
power estimator file of a fully or partially completed design from the Quartus II
software. After importing a file, you can edit some of the input parameters including
VCCINT, ambient temperature, airflow, clock frequency, and toggle percentage to suit
your system requirements.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP1C3T100C6 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone I 291 LABs 65 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP1C3T100C6ES | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Cyclone FPGA Family Data Sheet |
| EP1C3T100C6N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone I 291 LABs 65 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP1C3T100C7 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone I 291 LABs 65 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP1C3T100C7ES | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Cyclone FPGA Family Data Sheet |
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