參數(shù)資料
型號(hào)： EP1C6T324C6
廠商： Altera Corporation
英文描述： Cyclone FPGA Family
中文描述： 氣旋FPGA系列
文件頁數(shù)： 12/94頁
文件大?。?/td> 1138K
代理商： EP1C6T324C6
12
Altera Corporation
Cyclone FPGA Family Data Sheet
Preliminary Information
Normal Mode
The normal mode is suitable for general logic applications and
combinatorial functions. In normal mode, four data inputs from the LAB
local interconnect are inputs to a four-input LUT (see
Figure 6
). The
Quartus II Compiler automatically selects the carry-in or the
data3
signal
as one of the inputs to the LUT. Each LE can use LUT chain connections to
drive its combinatorial output directly to the next LE in the LAB.
Asynchronous load data for the register comes from the
data3
input of
the LE. LEs in normal mode support packed registers.
Figure 6. LE in Normal Mode
Note to
Figure 6
:
(1)
This signal is only allowed in normal mode if the LE is at the end of an adder/subtractor chain.
data1
data2
data3
cin (from cout
of previous LE)
4-Input
LUT
data4
addnsub (LAB Wide)
clock (LAB Wide)
ena (LAB Wide)
aclr (LAB Wide)
aload
(LAB Wide)
ALD/PRE
ADATA
CLRN
D
Q
ENA
sclear
(LAB Wide)
sload
(LAB Wide)
Register chain
connection
LUT chain
connection
Register
chain output
Row, column, and
direct link routing
Row, column, and
direct link routing
Local routing
Register Feedback
(1)
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