4–92
Alt
e
ra
Corpo
ratio
n
Stratix
De
vice
H
a
ndb
oo
k,
V
o
lu
me
1
Jan
uar
y
200
6
Hig
h
-Sp
eed
I/O
Spe
c
ificat
ion
Table 4–126. High-Speed I/O Specifications for Wire-Bond Packages (Part 1 of 2)
Symbol
Conditions
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
fHSCLK (Clock
frequency)
(LVDS,LVPECL,
HyperTransport
technology)
fHSCLK = fHSDR / W
W = 4 to 30 (Serdes used)
10
156
10
115.5
10
115.5
MHz
W = 2 (Serdes bypass)
50
231
50
231
50
231
MHz
W = 2 (Serdes used)
150
312
150
231
150
231
MHz
W = 1 (Serdes bypass)
100
311
100
270
100
270
MHz
W = 1 (Serdes used)
300
624
300
462
300
462
MHz
fHSDR Device operation,
(LVDS,LVPECL,
HyperTransport
technology)
J = 10
300
624
300
462
300
462
Mbps
J = 8
300
624
300
462
300
462
Mbps
J = 7
300
624
300
462
300
462
Mbps
J = 4
300
624
300
462
300
462
Mbps
J = 2
100
462
100
462
100
462
Mbps
J = 1 (LVDS and LVPECL
only)
100
311
100
270
100
270
Mbps
fHSCLK (Clock
frequency)
(PCML)
fHSCLK = fHSDR / W
W = 4 to 30 (Serdes used)
10
77.75
MHz
W = 2 (Serdes bypass)
50
150
50
77.5
50
77.5
MHz
W = 2 (Serdes used)
150
155.5
MHz
W = 1 (Serdes bypass)
100
200
100
155
100
155
MHz
W = 1 (Serdes used)
300
311
MHz
Device operation,
fHSDR
(PCML)
J = 10
300
311
Mbps
J = 8
300
311
Mbps
J = 7
300
311
Mbps
J = 4
300
311
Mbps
J = 2
100
300
100
155
100
155
Mbps
J = 1
100
200
100
155
100
155
Mbps
TCCS
All
400
ps