Altera Corporation
4–97
January 2006
Stratix Device Handbook, Volume 1
DC & Switching Characteristics
tOUTDUTY
Duty cycle for external clock output
(when set to 50%)
45
55
%
tJITTER
Period jitter for external clock output
±100 ps for >200-MHz outclk
±20 mUI for <200-MHz outclk
ps or
mUI
tCONFIG5,6
Time required to reconfigure the
scan chains for PLLs 5 and 6
289/fSCANCLK
tCONFIG11,12
Time required to reconfigure the
scan chains for PLLs 11 and 12
193/fSCANCLK
tSCANCLK
scanclk
22
MHz
tDLOCK
Time required to lock dynamically
(after switchover or reconfiguring any
non-post-scale counters/delays)
(7)100
μs
tLOCK
Time required to lock from end of
device configuration
(11)10
400
μs
fVCO
PLL internal VCO operating range
300
MHz
tLSKEW
Clock skew between two external
clock outputs driven by the same
counter
±50
ps
tSKEW
Clock skew between two external
clock outputs driven by the different
counters with the same settings
±75
ps
fSS
Spread spectrum modulation
frequency
30
150
kHz
% spread
Percentage spread for spread
0.5
0.6
%
tARESET
Minimum pulse width on areset
signal
10
Table 4–130. Enhanced PLL Specifications for -8 Speed Grade (Part 1 of 3)
Symbol
Parameter
Min
Typ
Max
Unit
fIN
Input clock frequency
3
480
MHz
fINPFD
Input frequency to PFD
3
420
MHz
fINDUTY
Input clock duty cycle
40
60
%
fEINDUTY
External feedback clock input duty
cycle
40
60
%
tINJITTER
Input clock period jitter
ps
Table 4–129. Enhanced PLL Specifications for -7 Speed Grade (Part 2 of 2)
Symbol
Parameter
Min
Typ
Max
Unit